// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
// Netlist written on Wed Feb 03 11:57:59 2021
//
// Verilog Description of module oled_top
//

module oled_top (sck, miso, reset_oled, clk, dc, sck_reg) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(23[8:16])
    output sck;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(24[12:15])
    output miso;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(26[12:16])
    output reset_oled;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(28[16:26])
    input clk;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    output dc;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(30[12:14])
    output sck_reg;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(31[12:19])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    wire sck_reg_c /* synthesis is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(31[12:19])
    wire write_start_N_216 /* synthesis is_clock=1, SET_AS_NETWORK=write_start_N_216 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(103[9:20])
    wire spi_send_N_206 /* synthesis is_clock=1, SET_AS_NETWORK=spi_send_N_206 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(59[9:17])
    
    wire GND_net, VCC_net, sck_c, miso_c, reset_oled_c, dc_c_0;
    wire [31:0]reset_count;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(34[15:26])
    
    wire spi_send;
    wire [7:0]spi_data_out;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(60[14:26])
    
    wire n6402;
    wire [7:0]spi_data_init;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(82[15:28])
    
    wire init_done, spi_send_write;
    wire [7:0]spi_data_write;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(98[15:29])
    
    wire n5931, clk_c_enable_64;
    wire [7:0]set_pos_y;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(102[24:33])
    
    wire write_start, spi_send_clear, n5930;
    wire [7:0]spi_data_clear;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(105[15:29])
    
    wire n6932;
    wire [5:0]cur_st;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(143[14:20])
    
    wire n5929, reset_count_31__N_163, n3948, n6408, n5939, n19, 
        reset_oled_N_181, reset_n_N_186, n5938;
    wire [31:0]nxt_st_5__N_164;
    
    wire n6354, n6810, n6931, n5983, n6930, n6929, dc_in_N_211, 
        spi_send_N_200, n667, n668, n669, n670, n671, n672, n673;
    wire [7:0]spi_data_out_7__N_171;
    wire [7:0]spi_data_out_7__N_33;
    
    wire spi_send_N_191, n6964, n5928, n5937, n5936, n3865, n5924, 
        n6928, n20, n19_adj_605, n5935, sck_N_335, n6395, nxt_st_4__N_226, 
        n13, n6510, miso_N_337, n5934, n6502, n5927, n5926, spi_data_7__N_346, 
        spi_data_7__N_348, spi_data_7__N_350, spi_data_7__N_352, spi_data_7__N_354, 
        spi_data_7__N_355, n6488;
    wire [47:0]write_data_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(46[15:29])
    
    wire n6460;
    wire [3:0]cur_st_adj_633;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(48[14:20])
    wire [3:0]nxt_st_adj_634;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(48[21:27])
    wire [31:0]nxt_st_3__N_468;
    
    wire n6, n10;
    wire [3:0]nxt_st_3__N_472;
    
    wire n6922, n5, n8;
    wire [47:0]write_data_tmp_47__N_406;
    
    wire n6919;
    wire [3:0]cur_st_adj_650;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(45[14:20])
    
    wire n6500;
    wire [3:0]nxt_st_adj_651;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(45[21:27])
    
    wire n6918, n6917, n5925;
    wire [3:0]nxt_st_3__N_560;
    
    wire n6365, n6916, spi_data_7__N_521, n78, n5266, clk_c_enable_92, 
        n6913, n6912, n165, n164, n163, n162, n161, n160, n159, 
        n158, n157, n156, n155, n154, n153, n3299, n152, n151, 
        n150, n149, n148, n147, n146, n145, n144, n143, n24, 
        n142, n18, n141, n140, n139, n138, n6419, n6418, n137, 
        n136, n135, n134, clk_c_enable_62, n41, n6403, n6894, 
        n6444, n3291, n3312, n6911, n6910, cur_st_0_derived_8, n6908, 
        n6399, n6907, n3966, n6906, n6470, n3963, n6390, n14, 
        n3597, clk_c_enable_51, n6618, n6436, n23, n6890, clk_c_enable_91, 
        n6889, n6888, n6445, clk_c_enable_97, n3885, n6443, n4, 
        n6_adj_617, n3497, n6905, n10_adj_618, n32, n6904, n6974, 
        n29, n6859, n6902, n7234, n7232, n20_adj_619, n6957, n6956, 
        n6955, n6954, n6953, n5933, n6539, n6901, n6952, n6951, 
        n5932, n6973, n6971, n6950, n28, n6949, n7233, clk_c_enable_93, 
        n6899, n30, n6898, n6897, n6837, n6893, n6970, n6941, 
        n3646, n6968, clk_c_enable_14, n6939, n6967, n6965, n6442, 
        n6530, clk_c_enable_35, n6937, n26, n6936, n5988, n6935, 
        n5247, n9, n6417, n21, n6933;
    
    LUT4 i4_4_lut (.A(reset_count[10]), .B(n6488), .C(n6354), .D(n6436), 
         .Z(n10)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(44[12:27])
    defparam i4_4_lut.init = 16'hfffb;
    LUT4 i4537_2_lut (.A(reset_count[1]), .B(reset_count[3]), .Z(n6488)) /* synthesis lut_function=(A (B)) */ ;
    defparam i4537_2_lut.init = 16'h8888;
    FD1S3AX reset_n_141 (.D(reset_n_N_186), .CK(clk_c), .Q(set_pos_y[1]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(43[11] 57[24])
    defparam reset_n_141.GSR = "DISABLED";
    FD1S1A write_start_I_0 (.D(spi_send_N_200), .CK(write_start_N_216), 
           .Q(write_start));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(170[5] 223[16])
    defparam write_start_I_0.GSR = "ENABLED";
    IB clk_pad (.I(clk), .O(clk_c));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    FD1S1A spi_send_I_0 (.D(spi_send_N_191), .CK(spi_send_N_206), .Q(spi_send));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(246[9] 251[43])
    defparam spi_send_I_0.GSR = "ENABLED";
    LUT4 m1_lut (.Z(n7234)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
    defparam m1_lut.init = 16'hffff;
    CCU2D reset_count_1103_add_4_5 (.A0(reset_count[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(reset_count[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5925), .COUT(n5926), .S0(n162), .S1(n161));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_5.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_5.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_5.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_5.INJECT1_1 = "NO";
    PFUMX i4764 (.BLUT(n6964), .ALUT(n6965), .C0(cur_st_adj_650[0]), .Z(nxt_st_adj_651[0]));
    LUT4 i1561_4_lut_then_4_lut (.A(cur_st_adj_650[3]), .B(cur_st_adj_650[1]), 
         .C(cur_st_adj_650[2]), .D(cur_st_adj_650[0]), .Z(n6968)) /* synthesis lut_function=(!(A+(B (C+(D))+!B (C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i1561_4_lut_then_4_lut.init = 16'h0104;
    FD1S3IX reset_count_1103__i31 (.D(n134), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i31.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i30 (.D(n135), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i30.GSR = "DISABLED";
    CCU2D reset_count_1103_add_4_17 (.A0(reset_count[15]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[16]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5931), .COUT(n5932), .S0(n150), 
          .S1(n149));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_17.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_17.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_17.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_17.INJECT1_1 = "NO";
    FD1S3IX reset_count_1103__i29 (.D(n136), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i29.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i28 (.D(n137), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i28.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i27 (.D(n138), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i27.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i26 (.D(n139), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i26.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i25 (.D(n140), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i25.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i24 (.D(n141), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i24.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i23 (.D(n142), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i23.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i22 (.D(n143), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i22.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i21 (.D(n144), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i21.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i20 (.D(n145), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i20.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i19 (.D(n146), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i19.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i18 (.D(n147), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i18.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i17 (.D(n148), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i17.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i16 (.D(n149), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i16.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i15 (.D(n150), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i15.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i14 (.D(n151), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i14.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i13 (.D(n152), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i13.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i12 (.D(n153), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i12.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i11 (.D(n154), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i11.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i10 (.D(n155), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i10.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i9 (.D(n156), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i9.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i8 (.D(n157), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i8.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i7 (.D(n158), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i7.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i6 (.D(n159), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i6.GSR = "DISABLED";
    OB sck_reg_pad (.I(sck_reg_c), .O(sck_reg));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(31[12:19])
    FD1S3JX reset_count_1103__i5 (.D(n160), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i5.GSR = "DISABLED";
    FD1S3JX reset_count_1103__i4 (.D(n161), .CK(clk_c), .PD(reset_count_31__N_163), 
            .Q(reset_count[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i4.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i3 (.D(n162), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i3.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i2 (.D(n163), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i2.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i1 (.D(n164), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i1.GSR = "DISABLED";
    FD1S3IX reset_count_1103__i0 (.D(n165), .CK(clk_c), .CD(reset_count_31__N_163), 
            .Q(reset_count[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103__i0.GSR = "DISABLED";
    OB dc_pad (.I(dc_c_0), .O(dc));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(30[12:14])
    OB reset_oled_pad (.I(reset_oled_c), .O(reset_oled));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(28[16:26])
    OB miso_pad (.I(miso_c), .O(miso));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(26[12:16])
    OB sck_pad (.I(sck_c), .O(sck));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(24[12:15])
    PFUMX spi_data_out_7__I_9_i7 (.BLUT(spi_data_init[6]), .ALUT(spi_data_out_7__N_171[6]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[6]));
    FD1P3IX cur_st_i0_i5 (.D(nxt_st_5__N_164[5]), .SP(clk_c_enable_97), 
            .CD(n3966), .CK(clk_c), .Q(cur_st[5])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i5.GSR = "DISABLED";
    FD1P3IX cur_st_i0_i4 (.D(nxt_st_5__N_164[4]), .SP(clk_c_enable_97), 
            .CD(n3966), .CK(clk_c), .Q(cur_st[4])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i4.GSR = "DISABLED";
    FD1P3IX cur_st_i0_i3 (.D(n6418), .SP(clk_c_enable_97), .CD(n3948), 
            .CK(clk_c), .Q(cur_st[3])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i3.GSR = "DISABLED";
    FD1P3IX cur_st_i0_i2 (.D(n6931), .SP(clk_c_enable_97), .CD(n3966), 
            .CK(clk_c), .Q(cur_st[2])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i2.GSR = "DISABLED";
    FD1P3IX cur_st_i0_i1 (.D(nxt_st_5__N_164[1]), .SP(clk_c_enable_97), 
            .CD(n3966), .CK(clk_c), .Q(cur_st[1])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i1.GSR = "DISABLED";
    LUT4 i1224_2_lut_rep_92_3_lut (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[2]), 
         .Z(n6930)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1224_2_lut_rep_92_3_lut.init = 16'h8080;
    LUT4 i3333_2_lut_rep_114 (.A(cur_st[5]), .B(cur_st[4]), .Z(n6952)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3333_2_lut_rep_114.init = 16'heeee;
    PFUMX spi_data_out_7__I_9_i2 (.BLUT(spi_data_init[1]), .ALUT(spi_data_out_7__N_171[1]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[1]));
    LUT4 i1_3_lut_4_lut (.A(cur_st[5]), .B(cur_st[4]), .C(cur_st[3]), 
         .D(cur_st[0]), .Z(n21)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;
    defparam i1_3_lut_4_lut.init = 16'hfeee;
    LUT4 equal_189_i7_2_lut_rep_120 (.A(cur_st[1]), .B(cur_st[2]), .Z(n7232)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(243[21:30])
    defparam equal_189_i7_2_lut_rep_120.init = 16'heeee;
    LUT4 mux_105_i7_4_lut (.A(n3312), .B(spi_data_write[6]), .C(n6919), 
         .D(n6897), .Z(n667)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(243[18] 244[42])
    defparam mux_105_i7_4_lut.init = 16'hc0ca;
    LUT4 mux_105_i2_3_lut_4_lut (.A(n6899), .B(n3312), .C(n6919), .D(spi_data_write[1]), 
         .Z(n672)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i2_3_lut_4_lut.init = 16'hf404;
    LUT4 i1600_4_lut (.A(set_pos_y[1]), .B(n5), .C(cur_st[3]), .D(n6952), 
         .Z(n3312)) /* synthesis lut_function=(A (B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(244[18:42])
    defparam i1600_4_lut.init = 16'haa8a;
    LUT4 i1_2_lut_rep_79_3_lut_4_lut (.A(cur_st[5]), .B(cur_st[4]), .C(cur_st[0]), 
         .D(cur_st[3]), .Z(n6917)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_79_3_lut_4_lut.init = 16'hfffe;
    LUT4 mux_105_i6_3_lut_4_lut (.A(n6899), .B(n3312), .C(n6919), .D(spi_data_write[5]), 
         .Z(n668)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i6_3_lut_4_lut.init = 16'hf404;
    LUT4 i4567_2_lut_rep_94_3_lut (.A(cur_st[5]), .B(cur_st[4]), .C(cur_st[3]), 
         .Z(n6932)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i4567_2_lut_rep_94_3_lut.init = 16'hfefe;
    PFUMX spi_data_out_7__I_9_i6 (.BLUT(spi_data_init[5]), .ALUT(spi_data_out_7__N_171[5]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[5]));
    LUT4 i1_4_lut_4_lut (.A(cur_st_adj_650[0]), .B(cur_st_adj_650[2]), .C(cur_st_adj_650[3]), 
         .D(cur_st_adj_650[1]), .Z(n14)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C+(D))+!B (C+!(D))))) */ ;
    defparam i1_4_lut_4_lut.init = 16'h0306;
    LUT4 i3446_3_lut_4_lut (.A(n6917), .B(n6953), .C(n6912), .D(n3646), 
         .Z(n3291)) /* synthesis lut_function=(A (C (D))+!A (B (C (D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam i3446_3_lut_4_lut.init = 16'hf100;
    LUT4 i4627_2_lut_rep_71_3_lut_4_lut_4_lut_4_lut (.A(cur_st_adj_633[3]), 
         .B(cur_st_adj_633[2]), .C(cur_st_adj_633[1]), .D(cur_st_adj_633[0]), 
         .Z(cur_st_0_derived_8)) /* synthesis lut_function=(!(A+(B (C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i4627_2_lut_rep_71_3_lut_4_lut_4_lut_4_lut.init = 16'h1115;
    LUT4 i16_4_lut (.A(n19_adj_605), .B(n32), .C(n28), .D(n20), .Z(n3865)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i16_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_78_3_lut_4_lut (.A(cur_st[5]), .B(cur_st[4]), .C(cur_st[0]), 
         .D(cur_st[3]), .Z(n6916)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
    defparam i1_2_lut_rep_78_3_lut_4_lut.init = 16'hffef;
    LUT4 i4704_2_lut_2_lut_3_lut_3_lut_4_lut_2_lut_3_lut_4_lut (.A(cur_st[1]), 
         .B(cur_st[2]), .C(n6952), .D(cur_st[3]), .Z(n6539)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(243[21:30])
    defparam i4704_2_lut_2_lut_3_lut_3_lut_4_lut_2_lut_3_lut_4_lut.init = 16'h0001;
    LUT4 i1559_4_lut_then_4_lut (.A(cur_st_adj_650[3]), .B(cur_st_adj_650[2]), 
         .C(cur_st_adj_650[1]), .D(cur_st_adj_650[0]), .Z(n6971)) /* synthesis lut_function=(!(A+(B (C+(D))+!B !(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i1559_4_lut_then_4_lut.init = 16'h1004;
    LUT4 i1559_4_lut_else_4_lut (.A(cur_st_adj_650[3]), .B(cur_st_adj_650[2]), 
         .C(cur_st_adj_650[1]), .D(cur_st_adj_650[0]), .Z(n6970)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i1559_4_lut_else_4_lut.init = 16'h1404;
    LUT4 i2_2_lut_3_lut_4_lut (.A(cur_st[5]), .B(cur_st[4]), .C(n6470), 
         .D(cur_st[3]), .Z(n8)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i2_2_lut_3_lut_4_lut.init = 16'h0010;
    LUT4 i1243_3_lut_4_lut (.A(cur_st[3]), .B(n6930), .C(cur_st[4]), .D(cur_st[5]), 
         .Z(nxt_st_5__N_164[5])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(154[40:48])
    defparam i1243_3_lut_4_lut.init = 16'h7f80;
    LUT4 i4640_4_lut_then_4_lut (.A(clk_c_enable_93), .B(cur_st_adj_650[1]), 
         .C(cur_st_adj_650[2]), .D(cur_st_adj_650[3]), .Z(n6974)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
    defparam i4640_4_lut_then_4_lut.init = 16'h0020;
    LUT4 i1_2_lut_rep_115 (.A(cur_st[1]), .B(cur_st[2]), .Z(n6953)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam i1_2_lut_rep_115.init = 16'hbbbb;
    LUT4 i4640_4_lut_else_4_lut (.A(clk_c_enable_93), .B(cur_st_adj_650[1]), 
         .C(cur_st_adj_650[2]), .D(cur_st_adj_650[3]), .Z(n6973)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i4640_4_lut_else_4_lut.init = 16'h0002;
    LUT4 mux_841_i38_3_lut_4_lut (.A(n6897), .B(n3646), .C(n6913), .D(write_data_tmp[29]), 
         .Z(write_data_tmp_47__N_406[37])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(43[11] 57[24])
    defparam mux_841_i38_3_lut_4_lut.init = 16'h4f40;
    LUT4 i4655_3_lut_3_lut (.A(n6898), .B(n6443), .C(reset_oled_N_181), 
         .Z(clk_c_enable_92)) /* synthesis lut_function=(A+!(B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(44[12:27])
    defparam i4655_3_lut_3_lut.init = 16'hbfbf;
    LUT4 i3319_2_lut_rep_63_3_lut_4_lut_4_lut_2_lut (.A(cur_st[2]), .B(n6917), 
         .Z(n6901)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam i3319_2_lut_rep_63_3_lut_4_lut_4_lut_2_lut.init = 16'hdddd;
    LUT4 i1_3_lut_4_lut_4_lut (.A(cur_st[1]), .B(cur_st[2]), .C(n6916), 
         .D(n6917), .Z(n6403)) /* synthesis lut_function=(A (D)+!A ((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam i1_3_lut_4_lut_4_lut.init = 16'hfb51;
    LUT4 i3315_2_lut_rep_116 (.A(cur_st[2]), .B(cur_st[0]), .Z(n6954)) /* synthesis lut_function=(A (B)) */ ;
    defparam i3315_2_lut_rep_116.init = 16'h8888;
    LUT4 mux_105_i1_3_lut_4_lut (.A(n6899), .B(n3312), .C(n6919), .D(spi_data_write[0]), 
         .Z(n673)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i1_3_lut_4_lut.init = 16'hf404;
    LUT4 i1_4_lut_4_lut_rep_117 (.A(cur_st[2]), .B(cur_st[0]), .C(cur_st[1]), 
         .D(n6932), .Z(n6955)) /* synthesis lut_function=(!(A (B (C+(D))+!B (D))+!A ((D)+!C))) */ ;
    defparam i1_4_lut_4_lut_rep_117.init = 16'h007a;
    LUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(cur_st[2]), .B(cur_st[0]), .C(cur_st[1]), 
         .D(n6932), .Z(n6402)) /* synthesis lut_function=(!(A (C+(D))+!A (((D)+!C)+!B))) */ ;
    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'h004a;
    LUT4 i4645_4_lut_rep_58 (.A(miso_N_337), .B(clk_c_enable_93), .C(sck_N_335), 
         .D(nxt_st_4__N_226), .Z(clk_c_enable_35)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i4645_4_lut_rep_58.init = 16'hccc8;
    LUT4 mux_841_i33_3_lut_4_lut (.A(n6897), .B(n3646), .C(n6913), .D(write_data_tmp[24]), 
         .Z(write_data_tmp_47__N_406[32])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(43[11] 57[24])
    defparam mux_841_i33_3_lut_4_lut.init = 16'h4f40;
    LUT4 i4657_2_lut_4_lut (.A(miso_N_337), .B(clk_c_enable_93), .C(sck_N_335), 
         .D(nxt_st_4__N_226), .Z(n3963)) /* synthesis lut_function=(!(A+!(B (C+(D))))) */ ;
    defparam i4657_2_lut_4_lut.init = 16'h4440;
    LUT4 i1_3_lut_rep_74_4_lut (.A(cur_st[0]), .B(n6932), .C(cur_st[2]), 
         .D(cur_st[1]), .Z(n6912)) /* synthesis lut_function=(!((B+(C (D)+!C !(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam i1_3_lut_rep_74_4_lut.init = 16'h0220;
    LUT4 i1_4_lut_4_lut_adj_50 (.A(clk_c_enable_93), .B(n13), .C(n6390), 
         .D(n6932), .Z(n19)) /* synthesis lut_function=(!(A (B (D)+!B ((D)+!C))+!A ((D)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i1_4_lut_4_lut_adj_50.init = 16'h00ec;
    LUT4 i4_4_lut_adj_51 (.A(reset_count[11]), .B(n5983), .C(n3885), .D(reset_count[12]), 
         .Z(n10_adj_618)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(49[17:35])
    defparam i4_4_lut_adj_51.init = 16'hfffb;
    LUT4 i3_4_lut (.A(reset_count[12]), .B(reset_count[4]), .C(reset_count[13]), 
         .D(reset_count[8]), .Z(n6354)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(54[17:35])
    defparam i3_4_lut.init = 16'hfffe;
    LUT4 mux_105_i5_3_lut_4_lut (.A(n6918), .B(n3312), .C(n6919), .D(spi_data_write[4]), 
         .Z(n669)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i5_3_lut_4_lut.init = 16'hf404;
    LUT4 mux_105_i4_3_lut_4_lut (.A(n6918), .B(n3312), .C(n6919), .D(spi_data_write[3]), 
         .Z(n670)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i4_3_lut_4_lut.init = 16'hf404;
    LUT4 mux_105_i3_3_lut_4_lut (.A(n6918), .B(n3312), .C(n6919), .D(spi_data_write[2]), 
         .Z(n671)) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam mux_105_i3_3_lut_4_lut.init = 16'hf404;
    LUT4 m0_lut (.Z(n7233)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
    defparam m0_lut.init = 16'h0000;
    LUT4 i1_2_lut_rep_80 (.A(cur_st[0]), .B(n6932), .C(cur_st[2]), .D(cur_st[1]), 
         .Z(n6918)) /* synthesis lut_function=(A+(B+!(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam i1_2_lut_rep_80.init = 16'hefff;
    LUT4 i4649_4_lut_rep_60_4_lut (.A(n6906), .B(n6445), .C(n10), .D(n6950), 
         .Z(n6898)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(44[12:27])
    defparam i4649_4_lut_rep_60_4_lut.init = 16'h0001;
    LUT4 i4678_4_lut (.A(clk_c_enable_93), .B(n78), .C(cur_st[3]), .D(set_pos_y[1]), 
         .Z(clk_c_enable_97)) /* synthesis lut_function=(A ((C+!(D))+!B)) */ ;
    defparam i4678_4_lut.init = 16'ha2aa;
    LUT4 n616_bdd_2_lut_4742_4_lut (.A(cur_st[0]), .B(n6932), .C(cur_st[2]), 
         .D(cur_st[1]), .Z(n6810)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam n616_bdd_2_lut_4742_4_lut.init = 16'h1200;
    LUT4 cur_st_2__bdd_4_lut_4726_4_lut (.A(cur_st[0]), .B(n6932), .C(cur_st[2]), 
         .D(cur_st[1]), .Z(spi_send_N_200)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[69:78])
    defparam cur_st_2__bdd_4_lut_4726_4_lut.init = 16'h0100;
    LUT4 mux_106_i8_4_lut (.A(spi_data_clear[5]), .B(spi_data_write[7]), 
         .C(n6907), .D(n6919), .Z(spi_data_out_7__N_171[7])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[18] 244[42])
    defparam mux_106_i8_4_lut.init = 16'hca0a;
    CCU2D reset_count_1103_add_4_15 (.A0(reset_count[13]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[14]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5930), .COUT(n5931), .S0(n152), 
          .S1(n151));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_15.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_15.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_15.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_15.INJECT1_1 = "NO";
    LUT4 mux_106_i3_4_lut (.A(spi_data_clear[2]), .B(n3497), .C(n6905), 
         .D(n6957), .Z(spi_data_out_7__N_171[2])) /* synthesis lut_function=(A (B+(C+(D)))+!A !(B (C)+!B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[18] 244[42])
    defparam mux_106_i3_4_lut.init = 16'hafac;
    LUT4 cur_st_3__bdd_4_lut (.A(cur_st[0]), .B(cur_st[2]), .C(n6929), 
         .D(cur_st[1]), .Z(n6889)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam cur_st_3__bdd_4_lut.init = 16'h0800;
    LUT4 i1_4_lut (.A(n6859), .B(n13), .C(n6952), .D(n6929), .Z(n78)) /* synthesis lut_function=(!(A (B (C)+!B (C+!(D)))+!A ((C)+!B))) */ ;
    defparam i1_4_lut.init = 16'h0e0c;
    LUT4 i3102_3_lut_4_lut (.A(n6897), .B(n3646), .C(n6913), .D(write_data_tmp[30]), 
         .Z(write_data_tmp_47__N_406[38])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(43[11] 57[24])
    defparam i3102_3_lut_4_lut.init = 16'h4f40;
    LUT4 i1_4_lut_adj_52 (.A(n6922), .B(init_done), .C(n6502), .D(n6530), 
         .Z(n20_adj_619)) /* synthesis lut_function=(A+!(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(249[18] 251[43])
    defparam i1_4_lut_adj_52.init = 16'habbb;
    LUT4 i2_2_lut (.A(reset_count[26]), .B(reset_count[17]), .Z(n19_adj_605)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2_2_lut.init = 16'heeee;
    LUT4 cur_st_3__bdd_2_lut (.A(cur_st[0]), .B(cur_st[2]), .Z(n6888)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam cur_st_3__bdd_2_lut.init = 16'h1111;
    CCU2D reset_count_1103_add_4_33 (.A0(reset_count[31]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5939), .S0(n134));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_33.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_33.INIT1 = 16'h0000;
    defparam reset_count_1103_add_4_33.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_33.INJECT1_1 = "NO";
    CCU2D reset_count_1103_add_4_31 (.A0(reset_count[29]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[30]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5938), .COUT(n5939), .S0(n136), 
          .S1(n135));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_31.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_31.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_31.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_31.INJECT1_1 = "NO";
    CCU2D reset_count_1103_add_4_29 (.A0(reset_count[27]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[28]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5937), .COUT(n5938), .S0(n138), 
          .S1(n137));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_29.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_29.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_29.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_29.INJECT1_1 = "NO";
    LUT4 i42_4_lut_4_lut (.A(n6907), .B(n6919), .C(spi_send_clear), .D(spi_send_write), 
         .Z(n23)) /* synthesis lut_function=(A (B (D))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam i42_4_lut_4_lut.init = 16'hd850;
    LUT4 i1_4_lut_adj_53 (.A(n41), .B(n6949), .C(n5988), .D(cur_st[1]), 
         .Z(n6390)) /* synthesis lut_function=(!(A (B (C+!(D))+!B (C (D)))+!A (C+!(D)))) */ ;
    defparam i1_4_lut_adj_53.init = 16'h0f22;
    LUT4 i15_4_lut (.A(n29), .B(reset_count[21]), .C(n26), .D(reset_count[24]), 
         .Z(n32)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i15_4_lut.init = 16'hfffe;
    LUT4 i4701_4_lut_4_lut (.A(n6918), .B(n7232), .C(n30), .D(n21), 
         .Z(spi_send_N_206)) /* synthesis lut_function=(!(A (B (C)+!B (C+(D))))) */ ;
    defparam i4701_4_lut_4_lut.init = 16'h5d5f;
    FD1P3JX reset_oled_140 (.D(reset_oled_N_181), .SP(clk_c_enable_92), 
            .PD(n6898), .CK(clk_c), .Q(reset_oled_c));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(43[11] 57[24])
    defparam reset_oled_140.GSR = "DISABLED";
    GSR GSR_INST (.GSR(set_pos_y[1]));
    LUT4 i1561_4_lut_else_4_lut (.A(cur_st_adj_650[3]), .B(cur_st_adj_650[1]), 
         .C(cur_st_adj_650[2]), .D(cur_st_adj_650[0]), .Z(n6967)) /* synthesis lut_function=(!(A+(B (C+(D))+!B !(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i1561_4_lut_else_4_lut.init = 16'h1104;
    LUT4 i4622_4_lut_4_lut (.A(cur_st_0_derived_8), .B(n6510), .C(n6908), 
         .D(clk_c_enable_93), .Z(clk_c_enable_64)) /* synthesis lut_function=(A (B (C (D)))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam i4622_4_lut_4_lut.init = 16'hc400;
    LUT4 i3422_2_lut_rep_56_3_lut_4_lut (.A(cur_st[2]), .B(n6910), .C(n3646), 
         .D(n6399), .Z(n6894)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C))+!A ((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[33:42])
    defparam i3422_2_lut_rep_56_3_lut_4_lut.init = 16'h20f0;
    LUT4 i34_4_lut (.A(n6470), .B(n6929), .C(cur_st[2]), .D(n6951), 
         .Z(n13)) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;
    defparam i34_4_lut.init = 16'hc505;
    LUT4 i4521_4_lut (.A(init_done), .B(cur_st[1]), .C(n6408), .D(cur_st[0]), 
         .Z(n6470)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B+(C (D)))) */ ;
    defparam i4521_4_lut.init = 16'hfcee;
    LUT4 i3471_2_lut_rep_59_3_lut_4_lut (.A(cur_st[2]), .B(n6910), .C(n6399), 
         .D(n6911), .Z(n6897)) /* synthesis lut_function=(A (B (C (D)))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[33:42])
    defparam i3471_2_lut_rep_59_3_lut_4_lut.init = 16'hd000;
    CCU2D reset_count_1103_add_4_27 (.A0(reset_count[25]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[26]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5936), .COUT(n5937), .S0(n140), 
          .S1(n139));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_27.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_27.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_27.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_27.INJECT1_1 = "NO";
    LUT4 i3300_2_lut (.A(spi_data_out_7__N_33[0]), .B(set_pos_y[1]), .Z(spi_data_out[0])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(240[18] 244[42])
    defparam i3300_2_lut.init = 16'h8888;
    LUT4 n2948_bdd_4_lut (.A(n6919), .B(n6928), .C(n6837), .D(n6907), 
         .Z(dc_in_N_211)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A ((D)+!C))) */ ;
    defparam n2948_bdd_4_lut.init = 16'h22f0;
    LUT4 i5_4_lut (.A(n9), .B(init_done), .C(n8), .D(cur_st[0]), .Z(n3948)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i5_4_lut.init = 16'h0080;
    LUT4 i1_4_lut_adj_54 (.A(n6395), .B(n6417), .C(cur_st[1]), .D(n6890), 
         .Z(n6418)) /* synthesis lut_function=(A (B)+!A !((C+!(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i1_4_lut_adj_54.init = 16'h8c88;
    LUT4 i2_4_lut (.A(n6933), .B(n6365), .C(cur_st_adj_633[1]), .D(cur_st_adj_633[0]), 
         .Z(n6395)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i2_4_lut.init = 16'h0040;
    PFUMX spi_data_out_7__I_9_i1 (.BLUT(spi_data_init[0]), .ALUT(spi_data_out_7__N_171[0]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[0]));
    LUT4 i1215_2_lut (.A(cur_st[1]), .B(cur_st[0]), .Z(nxt_st_5__N_164[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(154[40:48])
    defparam i1215_2_lut.init = 16'h6666;
    LUT4 i3_2_lut_3_lut_4_lut (.A(sck_reg_c), .B(n6904), .C(n7232), .D(set_pos_y[1]), 
         .Z(n9)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i3_2_lut_3_lut_4_lut.init = 16'h0400;
    LUT4 i1236_2_lut_3_lut_4_lut (.A(cur_st[2]), .B(n6951), .C(cur_st[4]), 
         .D(cur_st[3]), .Z(nxt_st_5__N_164[4])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(154[40:48])
    defparam i1236_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i3360_2_lut_3_lut_4_lut (.A(cur_st[2]), .B(n6910), .C(n6912), 
         .D(n6399), .Z(n5266)) /* synthesis lut_function=(!(A ((C+!(D))+!B)+!A (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[33:42])
    defparam i3360_2_lut_3_lut_4_lut.init = 16'h0d00;
    LUT4 i1_2_lut_rep_72_3_lut_4_lut (.A(cur_st[3]), .B(n6952), .C(cur_st[1]), 
         .D(cur_st[0]), .Z(n6910)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
    defparam i1_2_lut_rep_72_3_lut_4_lut.init = 16'hffef;
    LUT4 i1_2_lut_3_lut_4_lut (.A(sck_reg_c), .B(n6904), .C(n6952), .D(set_pos_y[1]), 
         .Z(n6417)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h0400;
    PFUMX spi_data_out_7__I_9_i4 (.BLUT(spi_data_init[3]), .ALUT(spi_data_out_7__N_171[3]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[3]));
    LUT4 i1_2_lut_rep_69_3_lut_4_lut (.A(cur_st[3]), .B(n6952), .C(n7232), 
         .D(cur_st[0]), .Z(n6907)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam i1_2_lut_rep_69_3_lut_4_lut.init = 16'hfeff;
    LUT4 mux_414_i1_4_lut (.A(nxt_st_3__N_472[0]), .B(cur_st_adj_633[0]), 
         .C(n6913), .D(n3597), .Z(nxt_st_adj_634[0])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam mux_414_i1_4_lut.init = 16'h3a0a;
    LUT4 i1_2_lut_3_lut_4_lut_adj_55 (.A(cur_st[3]), .B(n6952), .C(n6951), 
         .D(cur_st[2]), .Z(n6399)) /* synthesis lut_function=(!(A+(B+(C (D)+!C !(D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_55.init = 16'h0110;
    LUT4 mux_414_i3_4_lut (.A(nxt_st_3__N_472[0]), .B(nxt_st_3__N_468[2]), 
         .C(n6913), .D(n3597), .Z(nxt_st_adj_634[2])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam mux_414_i3_4_lut.init = 16'hc505;
    CCU2D reset_count_1103_add_4_25 (.A0(reset_count[23]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[24]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5935), .COUT(n5936), .S0(n142), 
          .S1(n141));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_25.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_25.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_25.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_25.INJECT1_1 = "NO";
    LUT4 mux_414_i2_4_lut (.A(nxt_st_3__N_472[0]), .B(nxt_st_3__N_468[1]), 
         .C(n6913), .D(n3597), .Z(nxt_st_adj_634[1])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam mux_414_i2_4_lut.init = 16'hc505;
    CCU2D reset_count_1103_add_4_13 (.A0(reset_count[11]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[12]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5929), .COUT(n5930), .S0(n154), 
          .S1(n153));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_13.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_13.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_13.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_13.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_67_3_lut_4_lut (.A(cur_st[3]), .B(n6952), .C(n7232), 
         .D(cur_st[0]), .Z(n6905)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_67_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_73_3_lut_4_lut (.A(cur_st[3]), .B(n6952), .C(n6953), 
         .D(cur_st[0]), .Z(n6911)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_73_3_lut_4_lut.init = 16'hfffe;
    LUT4 i4676_2_lut_rep_57_3_lut (.A(sck_reg_c), .B(n6904), .C(sck_N_335), 
         .Z(clk_c_enable_62)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i4676_2_lut_rep_57_3_lut.init = 16'h4040;
    LUT4 i4679_4_lut (.A(n6902), .B(sck_N_335), .C(spi_data_7__N_521), 
         .D(n14), .Z(n6618)) /* synthesis lut_function=(A (B+!(D))+!A !(B (C)+!B (C+(D)))) */ ;
    defparam i4679_4_lut.init = 16'h8caf;
    CCU2D reset_count_1103_add_4_11 (.A0(reset_count[9]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[10]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5928), .COUT(n5929), .S0(n156), 
          .S1(n155));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_11.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_11.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_11.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_11.INJECT1_1 = "NO";
    LUT4 i1222_2_lut_rep_93_3_lut (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[2]), 
         .Z(n6931)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;
    defparam i1222_2_lut_rep_93_3_lut.init = 16'h7878;
    LUT4 i2_3_lut_rep_64_4_lut (.A(n7232), .B(n6916), .C(n6939), .D(n6941), 
         .Z(n6902)) /* synthesis lut_function=(A (C+(D))+!A ((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam i2_3_lut_rep_64_4_lut.init = 16'hfff1;
    LUT4 i4680_2_lut_3_lut (.A(sck_reg_c), .B(n6904), .C(n6618), .Z(clk_c_enable_51)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i4680_2_lut_3_lut.init = 16'h4040;
    LUT4 mux_106_i5_3_lut_4_lut (.A(n7232), .B(n6916), .C(n669), .D(spi_data_clear[4]), 
         .Z(spi_data_out_7__N_171[4])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i5_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_106_i7_3_lut_4_lut (.A(n7232), .B(n6916), .C(n667), .D(spi_data_clear[6]), 
         .Z(spi_data_out_7__N_171[6])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i7_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_106_i6_3_lut_4_lut (.A(n7232), .B(n6916), .C(n668), .D(spi_data_clear[5]), 
         .Z(spi_data_out_7__N_171[5])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i6_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_106_i4_3_lut_4_lut (.A(n7232), .B(n6916), .C(n670), .D(spi_data_clear[3]), 
         .Z(spi_data_out_7__N_171[3])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i4_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_106_i1_3_lut_4_lut (.A(n7232), .B(n6916), .C(n673), .D(spi_data_clear[0]), 
         .Z(spi_data_out_7__N_171[0])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i1_3_lut_4_lut.init = 16'hf1e0;
    PFUMX spi_data_out_7__I_9_i5 (.BLUT(spi_data_init[4]), .ALUT(spi_data_out_7__N_171[4]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[4]));
    LUT4 i1_2_lut_rep_97 (.A(reset_count[7]), .B(reset_count[6]), .Z(n6935)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_97.init = 16'heeee;
    LUT4 mux_106_i2_3_lut_4_lut (.A(n7232), .B(n6916), .C(n672), .D(spi_data_clear[1]), 
         .Z(spi_data_out_7__N_171[1])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(241[21:30])
    defparam mux_106_i2_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i4652_3_lut_4_lut (.A(sck_reg_c), .B(n6904), .C(n19), .D(set_pos_y[1]), 
         .Z(n3966)) /* synthesis lut_function=(!(A+((C (D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i4652_3_lut_4_lut.init = 16'h0444;
    LUT4 i1_2_lut_rep_68_3_lut (.A(reset_count[7]), .B(reset_count[6]), 
         .C(n3865), .Z(n6906)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_68_3_lut.init = 16'hfefe;
    FD1P3JX cur_st_i0_i0 (.D(n6419), .SP(clk_c_enable_97), .PD(n3948), 
            .CK(clk_c), .Q(cur_st[0])) /* synthesis lse_init_val=0 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam cur_st_i0_i0.GSR = "DISABLED";
    LUT4 i1_4_lut_4_lut_adj_56 (.A(cur_st[2]), .B(n6917), .C(cur_st[1]), 
         .D(n6916), .Z(n30)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (C (D)))) */ ;
    defparam i1_4_lut_4_lut_adj_56.init = 16'he800;
    LUT4 i3_4_lut_adj_57 (.A(reset_count[11]), .B(n6354), .C(reset_count[9]), 
         .D(n6442), .Z(n6443)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(54[17:35])
    defparam i3_4_lut_adj_57.init = 16'hffdf;
    oled_clear oled_clear (.clk_c(clk_c), .clk_c_enable_91(clk_c_enable_91), 
            .GND_net(GND_net), .cur_st({cur_st_adj_650}), .clk_c_enable_51(clk_c_enable_51), 
            .\nxt_st[0] (nxt_st_adj_651[0]), .\spi_data_clear[0] (spi_data_clear[0]), 
            .spi_data_7__N_521(spi_data_7__N_521), .spi_send_clear(spi_send_clear), 
            .\spi_data_clear[1] (spi_data_clear[1]), .\spi_data_clear[2] (spi_data_clear[2]), 
            .\spi_data_clear[3] (spi_data_clear[3]), .\spi_data_clear[4] (spi_data_clear[4]), 
            .\spi_data_clear[5] (spi_data_clear[5]), .n7233(n7233), .\spi_data_clear[6] (spi_data_clear[6]), 
            .\nxt_st[2] (nxt_st_adj_651[2]), .\nxt_st[1] (nxt_st_adj_651[1]), 
            .\nxt_st_3__N_560[0] (nxt_st_3__N_560[0]), .n6939(n6939), .n6941(n6941), 
            .n6408(n6408), .n6837(n6837)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(124[16] 136[6])
    LUT4 i1_4_lut_adj_58 (.A(n6898), .B(set_pos_y[1]), .C(n6444), .D(reset_oled_N_181), 
         .Z(reset_n_N_186)) /* synthesis lut_function=(A+(B ((D)+!C)+!B !(C))) */ ;
    defparam i1_4_lut_adj_58.init = 16'hefaf;
    LUT4 mux_405_i1_4_lut_then_4_lut (.A(nxt_st_3__N_560[0]), .B(cur_st_adj_650[1]), 
         .C(cur_st_adj_650[3]), .D(cur_st_adj_650[2]), .Z(n6965)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam mux_405_i1_4_lut_then_4_lut.init = 16'h0200;
    LUT4 i3_4_lut_adj_59 (.A(n5983), .B(n6436), .C(reset_count[12]), .D(n6442), 
         .Z(n6444)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(44[12:27])
    defparam i3_4_lut_adj_59.init = 16'hffdf;
    PFUMX i41 (.BLUT(n20_adj_619), .ALUT(n23), .C0(n6905), .Z(spi_send_N_191));
    LUT4 i1_2_lut_3_lut (.A(sck_reg_c), .B(n6904), .C(cur_st_adj_633[1]), 
         .Z(n4)) /* synthesis lut_function=(A+((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i1_2_lut_3_lut.init = 16'hfbfb;
    LUT4 mux_405_i1_4_lut_else_4_lut (.A(cur_st_adj_650[1]), .B(n6907), 
         .C(cur_st_adj_650[3]), .D(cur_st_adj_650[2]), .Z(n6964)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C+!(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(152[9] 163[16])
    defparam mux_405_i1_4_lut_else_4_lut.init = 16'h050b;
    PFUMX spi_data_out_7__I_9_i3 (.BLUT(n671), .ALUT(spi_data_out_7__N_171[2]), 
          .C0(n6539), .Z(spi_data_out_7__N_33[2]));
    PFUMX i4758 (.BLUT(n6889), .ALUT(n6888), .C0(cur_st[3]), .Z(n6890));
    LUT4 i1446_2_lut_3_lut_4_lut (.A(sck_reg_c), .B(n6904), .C(spi_data_7__N_355), 
         .D(sck_N_335), .Z(clk_c_enable_14)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(145[11] 147[29])
    defparam i1446_2_lut_3_lut_4_lut.init = 16'h4000;
    LUT4 i2_3_lut (.A(reset_count[8]), .B(reset_count[4]), .C(reset_count[13]), 
         .Z(n5983)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut.init = 16'h8080;
    PFUMX spi_data_out_7__I_9_i8 (.BLUT(spi_data_init[7]), .ALUT(spi_data_out_7__N_171[7]), 
          .C0(n6905), .Z(spi_data_out_7__N_33[7]));
    LUT4 i1_2_lut (.A(reset_count[11]), .B(reset_count[9]), .Z(n6436)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(44[12:27])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i1_3_lut (.A(n3885), .B(reset_count[14]), .C(reset_count[5]), 
         .Z(n6442)) /* synthesis lut_function=(A+!(B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(54[17:35])
    defparam i1_3_lut.init = 16'hbfbf;
    CCU2D reset_count_1103_add_4_9 (.A0(reset_count[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(reset_count[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5927), .COUT(n5928), .S0(n158), .S1(n157));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_9.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_9.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_9.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_9.INJECT1_1 = "NO";
    LUT4 i4_4_lut_adj_60 (.A(reset_count[10]), .B(n6445), .C(n6906), .D(n6), 
         .Z(n3885)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;
    defparam i4_4_lut_adj_60.init = 16'hfffd;
    LUT4 i4_4_lut_adj_61 (.A(cur_st[3]), .B(n6417), .C(n7232), .D(n6460), 
         .Z(n6419)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i4_4_lut_adj_61.init = 16'h0040;
    LUT4 i1_2_lut_rep_61_3_lut_4_lut (.A(cur_st[1]), .B(n6917), .C(n6399), 
         .D(cur_st[2]), .Z(n6899)) /* synthesis lut_function=(A (B (C)+!B !((D)+!C))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[33:42])
    defparam i1_2_lut_rep_61_3_lut_4_lut.init = 16'hd0f0;
    LUT4 i1_2_lut_adj_62 (.A(reset_count[1]), .B(reset_count[3]), .Z(n6)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_adj_62.init = 16'heeee;
    CCU2D reset_count_1103_add_4_3 (.A0(reset_count[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(reset_count[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5924), .COUT(n5925), .S0(n164), .S1(n163));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_3.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_3.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_3.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_3.INJECT1_1 = "NO";
    CCU2D reset_count_1103_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(reset_count[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n5924), .S1(n165));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_1.INIT0 = 16'hF000;
    defparam reset_count_1103_add_4_1.INIT1 = 16'h0555;
    defparam reset_count_1103_add_4_1.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_1.INJECT1_1 = "NO";
    CCU2D reset_count_1103_add_4_23 (.A0(reset_count[21]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[22]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5934), .COUT(n5935), .S0(n144), 
          .S1(n143));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_23.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_23.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_23.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_23.INJECT1_1 = "NO";
    CCU2D reset_count_1103_add_4_7 (.A0(reset_count[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(reset_count[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5926), .COUT(n5927), .S0(n160), .S1(n159));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_7.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_7.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_7.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_7.INJECT1_1 = "NO";
    LUT4 i4551_4_lut (.A(spi_data_7__N_355), .B(n6936), .C(n6956), .D(n6937), 
         .Z(n6502)) /* synthesis lut_function=(A+(B ((D)+!C))) */ ;
    defparam i4551_4_lut.init = 16'heeae;
    CCU2D reset_count_1103_add_4_21 (.A0(reset_count[19]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[20]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5933), .COUT(n5934), .S0(n146), 
          .S1(n145));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_21.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_21.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_21.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_21.INJECT1_1 = "NO";
    LUT4 i4578_4_lut (.A(spi_data_7__N_350), .B(spi_data_7__N_352), .C(spi_data_7__N_346), 
         .D(n6500), .Z(n6530)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i4578_4_lut.init = 16'hfffe;
    LUT4 i3441_2_lut_3_lut_4_lut (.A(cur_st[1]), .B(n6917), .C(n3646), 
         .D(cur_st[2]), .Z(n3299)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(242[33:42])
    defparam i3441_2_lut_3_lut_4_lut.init = 16'h2000;
    LUT4 i4549_2_lut (.A(spi_data_7__N_354), .B(spi_data_7__N_348), .Z(n6500)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i4549_2_lut.init = 16'heeee;
    LUT4 i1_4_lut_adj_63 (.A(n24), .B(n3865), .C(n6_adj_617), .D(reset_count[13]), 
         .Z(reset_count_31__N_163)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i1_4_lut_adj_63.init = 16'heccc;
    LUT4 i1180_4_lut (.A(n18), .B(reset_count[11]), .C(reset_count[10]), 
         .D(reset_count[9]), .Z(n24)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1180_4_lut.init = 16'hfcec;
    LUT4 i2_2_lut_adj_64 (.A(reset_count[14]), .B(reset_count[12]), .Z(n6_adj_617)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut_adj_64.init = 16'h8888;
    LUT4 i1_2_lut_adj_65 (.A(reset_count[0]), .B(reset_count[2]), .Z(n6445)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_adj_65.init = 16'heeee;
    LUT4 i1200_4_lut (.A(reset_count[4]), .B(reset_count[8]), .C(n6935), 
         .D(reset_count[5]), .Z(n18)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1200_4_lut.init = 16'hc8c0;
    LUT4 i11_4_lut (.A(reset_count[29]), .B(reset_count[22]), .C(reset_count[30]), 
         .D(reset_count[25]), .Z(n28)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i11_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_adj_66 (.A(cur_st[1]), .B(cur_st[2]), .C(cur_st[0]), 
         .Z(n5)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(243[21:30])
    defparam i1_2_lut_3_lut_adj_66.init = 16'hfefe;
    LUT4 i3_2_lut (.A(reset_count[18]), .B(reset_count[23]), .Z(n20)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3_2_lut.init = 16'heeee;
    LUT4 i12_4_lut (.A(reset_count[28]), .B(reset_count[15]), .C(reset_count[31]), 
         .D(reset_count[27]), .Z(n29)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i12_4_lut.init = 16'hfffe;
    LUT4 i3341_2_lut_4_lut (.A(n6916), .B(cur_st[1]), .C(cur_st[2]), .D(n6955), 
         .Z(n5247)) /* synthesis lut_function=(A (D)+!A (B (C (D))+!B !(C+!(D)))) */ ;
    defparam i3341_2_lut_4_lut.init = 16'heb00;
    LUT4 i1_2_lut_rep_81_3_lut_4_lut (.A(cur_st[1]), .B(cur_st[2]), .C(n6952), 
         .D(cur_st[3]), .Z(n6919)) /* synthesis lut_function=(!(A (C+(D))+!A ((C+(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(243[21:30])
    defparam i1_2_lut_rep_81_3_lut_4_lut.init = 16'h000e;
    LUT4 i9_3_lut (.A(reset_count[16]), .B(reset_count[20]), .C(reset_count[19]), 
         .Z(n26)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i9_3_lut.init = 16'hfefe;
    LUT4 i1_4_lut_4_lut_4_lut_4_lut (.A(cur_st[0]), .B(cur_st[2]), .C(n6932), 
         .D(cur_st[1]), .Z(write_start_N_216)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A ((C)+!B)) */ ;
    defparam i1_4_lut_4_lut_4_lut_4_lut.init = 16'hf1f3;
    LUT4 i4509_2_lut_3_lut_rep_111 (.A(cur_st[0]), .B(cur_st[2]), .C(init_done), 
         .Z(n6949)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i4509_2_lut_3_lut_rep_111.init = 16'h1010;
    LUT4 cur_st_0__bdd_4_lut_3_lut (.A(cur_st[0]), .B(cur_st[2]), .C(cur_st[1]), 
         .Z(n6859)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(B+(C)))) */ ;
    defparam cur_st_0__bdd_4_lut_3_lut.init = 16'h7c7c;
    LUT4 i1_2_lut_rep_112 (.A(reset_count[14]), .B(reset_count[5]), .Z(n6950)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(49[17:35])
    defparam i1_2_lut_rep_112.init = 16'heeee;
    LUT4 i5_3_lut_4_lut (.A(reset_count[14]), .B(reset_count[5]), .C(n10_adj_618), 
         .D(reset_count[9]), .Z(reset_oled_N_181)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(49[17:35])
    defparam i5_3_lut_4_lut.init = 16'hfeff;
    LUT4 i1_2_lut_rep_113 (.A(cur_st[1]), .B(cur_st[0]), .Z(n6951)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_113.init = 16'h8888;
    CCU2D reset_count_1103_add_4_19 (.A0(reset_count[17]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(reset_count[18]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5932), .COUT(n5933), .S0(n148), 
          .S1(n147));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(41[27:40])
    defparam reset_count_1103_add_4_19.INIT0 = 16'hfaaa;
    defparam reset_count_1103_add_4_19.INIT1 = 16'hfaaa;
    defparam reset_count_1103_add_4_19.INJECT1_0 = "NO";
    defparam reset_count_1103_add_4_19.INJECT1_1 = "NO";
    LUT4 i2_2_lut_3_lut_4_lut_adj_67 (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[3]), 
         .D(cur_st[2]), .Z(n6365)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i2_2_lut_3_lut_4_lut_adj_67.init = 16'h0800;
    spi_master spi_master (.n2954({Open_0, Open_1, Open_2, sck_N_335}), 
            .clk_c(clk_c), .clk_c_enable_93(clk_c_enable_93), .sck_reg_c(sck_reg_c), 
            .GND_net(GND_net), .\spi_data_out[0] (spi_data_out[0]), .clk_c_enable_35(clk_c_enable_35), 
            .n3963(n3963), .miso_c(miso_c), .miso_N_337(miso_N_337), .n6904(n6904), 
            .spi_send(spi_send), .nxt_st_4__N_226(nxt_st_4__N_226), .\spi_data_out_7__N_33[7] (spi_data_out_7__N_33[7]), 
            .\set_pos_y[1] (set_pos_y[1]), .\spi_data_out_7__N_33[6] (spi_data_out_7__N_33[6]), 
            .\spi_data_out_7__N_33[5] (spi_data_out_7__N_33[5]), .\spi_data_out_7__N_33[4] (spi_data_out_7__N_33[4]), 
            .\spi_data_out_7__N_33[3] (spi_data_out_7__N_33[3]), .\spi_data_out_7__N_33[2] (spi_data_out_7__N_33[2]), 
            .\spi_data_out_7__N_33[1] (spi_data_out_7__N_33[1]), .dc_in_N_211(dc_in_N_211), 
            .n6905(n6905), .dc_c_0(dc_c_0), .sck_c(sck_c)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(65[16] 79[6])
    oled_init oled_init (.n2961({Open_3, Open_4, Open_5, Open_6, Open_7, 
            Open_8, Open_9, Open_10, Open_11, Open_12, Open_13, 
            init_done}), .clk_c(clk_c), .clk_c_enable_14(clk_c_enable_14), 
            .n7234(n7234), .n6922(n6922), .spi_data_7__N_350(spi_data_7__N_350), 
            .\spi_data_init[7] (spi_data_init[7]), .spi_data_7__N_348(spi_data_7__N_348), 
            .n6956(n6956), .n3497(n3497), .spi_data_7__N_346(spi_data_7__N_346), 
            .n6957(n6957), .\spi_data_init[4] (spi_data_init[4]), .\spi_data_init[6] (spi_data_init[6]), 
            .clk_c_enable_62(clk_c_enable_62), .n7233(n7233), .spi_data_7__N_352(spi_data_7__N_352), 
            .spi_data_7__N_354(spi_data_7__N_354), .spi_data_7__N_355(spi_data_7__N_355), 
            .\spi_data_init[1] (spi_data_init[1]), .n6936(n6936), .n6937(n6937), 
            .\cur_st[0] (cur_st[0]), .\cur_st[2] (cur_st[2]), .n6408(n6408), 
            .n41(n41), .\spi_data_init[0] (spi_data_init[0]), .\spi_data_init[3] (spi_data_init[3]), 
            .\spi_data_init[5] (spi_data_init[5])) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(86[15] 95[6])
    VLO i1 (.Z(GND_net));
    PFUMX i4770 (.BLUT(n6973), .ALUT(n6974), .C0(cur_st_adj_650[0]), .Z(clk_c_enable_91));
    TSALL TSALL_INST (.TSALL(GND_net));
    PFUMX i4768 (.BLUT(n6970), .ALUT(n6971), .C0(nxt_st_3__N_560[0]), 
          .Z(nxt_st_adj_651[2]));
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    PFUMX i4766 (.BLUT(n6967), .ALUT(n6968), .C0(nxt_st_3__N_560[0]), 
          .Z(nxt_st_adj_651[1]));
    oled_write_data oled_write_data (.clk_c(clk_c), .\set_pos_y[1] (set_pos_y[1]), 
            .spi_data_write({spi_data_write}), .\cur_st[0]_derived_8 (cur_st_0_derived_8), 
            .cur_st({cur_st_adj_633}), .clk_c_enable_64(clk_c_enable_64), 
            .\nxt_st[0] (nxt_st_adj_634[0]), .spi_send_write(spi_send_write), 
            .\write_data_tmp[29] (write_data_tmp[29]), .n7233(n7233), .n6901(n6901), 
            .n3646(n3646), .n6913(n6913), .n3291(n3291), .n4(n4), .n6899(n6899), 
            .n6933(n6933), .\nxt_st[2] (nxt_st_adj_634[2]), .\nxt_st[1] (nxt_st_adj_634[1]), 
            .n6810(n6810), .n6912(n6912), .\write_data_tmp_47__N_406[38] (write_data_tmp_47__N_406[38]), 
            .\write_data_tmp_47__N_406[37] (write_data_tmp_47__N_406[37]), 
            .\write_data_tmp_47__N_406[32] (write_data_tmp_47__N_406[32]), 
            .\write_data_tmp[30] (write_data_tmp[30]), .\write_data_tmp[24] (write_data_tmp[24]), 
            .n6893(n6893), .n3299(n3299), .n6894(n6894), .n6928(n6928), 
            .sck_N_335(sck_N_335), .n6510(n6510), .GND_net(GND_net), .n6954(n6954), 
            .n5988(n5988), .\cur_st[0] (cur_st[0]), .n6460(n6460), .sck_reg_c(sck_reg_c), 
            .n6904(n6904), .n6403(n6403), .\nxt_st_3__N_472[0] (nxt_st_3__N_472[0]), 
            .\nxt_st_3__N_468[2] (nxt_st_3__N_468[2]), .n6932(n6932), .n6951(n6951), 
            .\cur_st[2] (cur_st[2]), .n6929(n6929), .n5266(n5266), .n6402(n6402), 
            .spi_send_N_200(spi_send_N_200), .\nxt_st_3__N_468[1] (nxt_st_3__N_468[1]), 
            .write_start(write_start), .n6908(n6908), .n5247(n5247), .n3597(n3597)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(110[21] 122[6])
    LUT4 i1_2_lut_rep_55_3_lut_4_lut (.A(n6918), .B(n6911), .C(n3646), 
         .D(n6399), .Z(n6893)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C))+!A !(C))) */ ;
    defparam i1_2_lut_rep_55_3_lut_4_lut.init = 16'h70f0;
    VHI i4865 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module oled_clear
//

module oled_clear (clk_c, clk_c_enable_91, GND_net, cur_st, clk_c_enable_51, 
            \nxt_st[0] , \spi_data_clear[0] , spi_data_7__N_521, spi_send_clear, 
            \spi_data_clear[1] , \spi_data_clear[2] , \spi_data_clear[3] , 
            \spi_data_clear[4] , \spi_data_clear[5] , n7233, \spi_data_clear[6] , 
            \nxt_st[2] , \nxt_st[1] , \nxt_st_3__N_560[0] , n6939, n6941, 
            n6408, n6837) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    input clk_c_enable_91;
    input GND_net;
    output [3:0]cur_st;
    input clk_c_enable_51;
    input \nxt_st[0] ;
    output \spi_data_clear[0] ;
    output spi_data_7__N_521;
    output spi_send_clear;
    output \spi_data_clear[1] ;
    output \spi_data_clear[2] ;
    output \spi_data_clear[3] ;
    output \spi_data_clear[4] ;
    output \spi_data_clear[5] ;
    input n7233;
    output \spi_data_clear[6] ;
    input \nxt_st[2] ;
    input \nxt_st[1] ;
    output \nxt_st_3__N_560[0] ;
    output n6939;
    output n6941;
    output n6408;
    output n6837;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    wire spi_send_N_598 /* synthesis is_clock=1, SET_AS_NETWORK=\oled_clear/spi_send_N_598 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(25[16:24])
    wire [7:0]y_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(38[20:25])
    
    wire n3950;
    wire [7:0]n37;
    
    wire n5920;
    wire [7:0]x_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(38[14:19])
    wire [7:0]n695;
    
    wire n5921, n6924;
    wire [6:0]n2441;
    wire [6:0]n2426;
    
    wire spi_send_N_597, n6934, n3463, n6427, n6363, n5940, n3974, 
        n3959, n3859, n6926, n9, n14, n6532, n6528, n6496, n6942, 
        n5922, n5923, n5943, n5942, n5941;
    
    FD1P3IX y_tmp_1108__i2 (.D(n37[2]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i2.GSR = "ENABLED";
    CCU2D add_170_3 (.A0(x_tmp[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(x_tmp[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n5920), 
          .COUT(n5921), .S0(n695[1]), .S1(n695[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(106[29:36])
    defparam add_170_3.INIT0 = 16'h5aaa;
    defparam add_170_3.INIT1 = 16'h5aaa;
    defparam add_170_3.INJECT1_0 = "NO";
    defparam add_170_3.INJECT1_1 = "NO";
    CCU2D add_170_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(x_tmp[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n5920), 
          .S1(n695[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(106[29:36])
    defparam add_170_1.INIT0 = 16'hF000;
    defparam add_170_1.INIT1 = 16'h5555;
    defparam add_170_1.INJECT1_0 = "NO";
    defparam add_170_1.INJECT1_1 = "NO";
    FD1P3AX cur_st_i0_i0 (.D(\nxt_st[0] ), .SP(clk_c_enable_51), .CK(clk_c), 
            .Q(cur_st[0])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam cur_st_i0_i0.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i1 (.D(n2441[0]), .CK(spi_data_7__N_521), .CD(n6924), 
           .Q(\spi_data_clear[0] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i1.GSR = "ENABLED";
    LUT4 mux_864_i3_3_lut (.A(x_tmp[6]), .B(n2426[2]), .C(cur_st[0]), 
         .Z(n2441[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_864_i3_3_lut.init = 16'hcaca;
    FD1S1A spi_send_I_0 (.D(spi_send_N_597), .CK(spi_send_N_598), .Q(spi_send_clear)) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_send_I_0.GSR = "ENABLED";
    LUT4 mux_856_i3_3_lut (.A(y_tmp[2]), .B(x_tmp[2]), .C(cur_st[1]), 
         .Z(n2426[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_856_i3_3_lut.init = 16'hcaca;
    LUT4 mux_864_i4_3_lut (.A(x_tmp[7]), .B(n2426[3]), .C(cur_st[0]), 
         .Z(n2441[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_864_i4_3_lut.init = 16'hcaca;
    LUT4 mux_856_i4_3_lut (.A(y_tmp[3]), .B(x_tmp[3]), .C(cur_st[1]), 
         .Z(n2426[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_856_i4_3_lut.init = 16'hcaca;
    FD1S1I spi_data_7__I_0_i2 (.D(n2441[1]), .CK(spi_data_7__N_521), .CD(n6924), 
           .Q(\spi_data_clear[1] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i2.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i3 (.D(n2441[2]), .CK(spi_data_7__N_521), .CD(n6924), 
           .Q(\spi_data_clear[2] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i3.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i4 (.D(n2441[3]), .CK(spi_data_7__N_521), .CD(n6924), 
           .Q(\spi_data_clear[3] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i4.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i5 (.D(n6934), .CK(spi_data_7__N_521), .CD(n6924), 
           .Q(\spi_data_clear[4] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i5.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i6 (.D(n3463), .CK(spi_data_7__N_521), .CD(cur_st[1]), 
           .Q(\spi_data_clear[5] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i6.GSR = "ENABLED";
    CCU2D y_tmp_1108_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(n6427), .B1(n6363), .C1(y_tmp[0]), .D1(GND_net), 
          .COUT(n5940), .S1(n37[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108_add_4_1.INIT0 = 16'hF000;
    defparam y_tmp_1108_add_4_1.INIT1 = 16'he1e1;
    defparam y_tmp_1108_add_4_1.INJECT1_0 = "NO";
    defparam y_tmp_1108_add_4_1.INJECT1_1 = "NO";
    FD1P3IX x_tmp_i0_i3 (.D(n695[3]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[3])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i3.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i2 (.D(n695[2]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i2.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i1 (.D(n695[1]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i1.GSR = "ENABLED";
    FD1P3AX cur_st_i0_i3 (.D(n7233), .SP(clk_c_enable_51), .CK(clk_c), 
            .Q(cur_st[3])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam cur_st_i0_i3.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i7 (.D(n695[7]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[7])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i7.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i6 (.D(n37[6]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i6.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i6 (.D(n695[6]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[6])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i6.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i7 (.D(n37[7]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i7.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i1 (.D(n37[1]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i1.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i5 (.D(n695[5]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[5])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i5.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i5 (.D(n37[5]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i5.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i7 (.D(n3859), .CK(spi_data_7__N_521), .CD(n3959), 
           .Q(\spi_data_clear[6] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(70[5] 83[20])
    defparam spi_data_7__I_0_i7.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i4 (.D(n37[4]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i4.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i0 (.D(n37[0]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i0.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i4 (.D(n695[4]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[4])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i4.GSR = "ENABLED";
    FD1P3IX y_tmp_1108__i3 (.D(n37[3]), .SP(clk_c_enable_91), .CD(n3950), 
            .CK(clk_c), .Q(y_tmp[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108__i3.GSR = "ENABLED";
    LUT4 i4615_2_lut_2_lut_3_lut_4_lut_4_lut (.A(cur_st[0]), .B(cur_st[1]), 
         .C(cur_st[3]), .D(cur_st[2]), .Z(spi_data_7__N_521)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i4615_2_lut_2_lut_3_lut_4_lut_4_lut.init = 16'h010f;
    LUT4 i1_4_lut_4_lut (.A(cur_st[1]), .B(cur_st[3]), .C(cur_st[2]), 
         .Z(spi_send_N_598)) /* synthesis lut_function=(!(A (B+(C))+!A (B))) */ ;
    defparam i1_4_lut_4_lut.init = 16'h1313;
    LUT4 i4642_2_lut_4_lut_4_lut_4_lut (.A(cur_st[0]), .B(cur_st[1]), .C(cur_st[2]), 
         .D(cur_st[3]), .Z(n3859)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i4642_2_lut_4_lut_4_lut_4_lut.init = 16'h0002;
    LUT4 i4675_2_lut_4_lut (.A(n6363), .B(n6926), .C(n6427), .D(clk_c_enable_91), 
         .Z(n3974)) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B !(C+!(D)))) */ ;
    defparam i4675_2_lut_4_lut.init = 16'hcd00;
    FD1P3AX cur_st_i0_i2 (.D(\nxt_st[2] ), .SP(clk_c_enable_51), .CK(clk_c), 
            .Q(cur_st[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam cur_st_i0_i2.GSR = "ENABLED";
    FD1P3AX cur_st_i0_i1 (.D(\nxt_st[1] ), .SP(clk_c_enable_51), .CK(clk_c), 
            .Q(cur_st[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam cur_st_i0_i1.GSR = "ENABLED";
    FD1P3IX x_tmp_i0_i0 (.D(n695[0]), .SP(clk_c_enable_91), .CD(n3974), 
            .CK(clk_c), .Q(x_tmp[0])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=124, LSE_RLINE=136 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(93[14] 108[16])
    defparam x_tmp_i0_i0.GSR = "ENABLED";
    LUT4 i2042_1_lut (.A(y_tmp[6]), .Z(n3959)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam i2042_1_lut.init = 16'h5555;
    LUT4 i7_4_lut (.A(n9), .B(n14), .C(y_tmp[6]), .D(x_tmp[1]), .Z(\nxt_st_3__N_560[0] )) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam i7_4_lut.init = 16'hfeff;
    LUT4 i1_2_lut (.A(y_tmp[4]), .B(y_tmp[3]), .Z(n9)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i6_4_lut (.A(x_tmp[7]), .B(y_tmp[5]), .C(y_tmp[7]), .D(n6532), 
         .Z(n14)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam i6_4_lut.init = 16'hfeff;
    LUT4 i4580_4_lut (.A(n6528), .B(x_tmp[2]), .C(n6496), .D(y_tmp[0]), 
         .Z(n6532)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i4580_4_lut.init = 16'h8000;
    LUT4 i4576_4_lut (.A(x_tmp[4]), .B(x_tmp[3]), .C(y_tmp[1]), .D(x_tmp[5]), 
         .Z(n6528)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i4576_4_lut.init = 16'h8000;
    LUT4 i4545_3_lut (.A(x_tmp[0]), .B(y_tmp[2]), .C(x_tmp[6]), .Z(n6496)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i4545_3_lut.init = 16'h8080;
    LUT4 i4684_2_lut_rep_96 (.A(cur_st[0]), .B(cur_st[1]), .Z(n6934)) /* synthesis lut_function=(!(A (B))) */ ;
    defparam i4684_2_lut_rep_96.init = 16'h7777;
    LUT4 mux_864_i1_3_lut (.A(x_tmp[4]), .B(n2426[0]), .C(cur_st[0]), 
         .Z(n2441[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_864_i1_3_lut.init = 16'hcaca;
    LUT4 mux_856_i1_3_lut (.A(y_tmp[0]), .B(x_tmp[0]), .C(cur_st[1]), 
         .Z(n2426[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_856_i1_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_101 (.A(cur_st[2]), .B(cur_st[3]), .Z(n6939)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i1_2_lut_rep_101.init = 16'heeee;
    LUT4 i2043_2_lut_3_lut_4_lut (.A(cur_st[0]), .B(cur_st[1]), .C(clk_c_enable_91), 
         .D(n6942), .Z(n3950)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i2043_2_lut_3_lut_4_lut.init = 16'hf0d0;
    LUT4 i1_2_lut_rep_103 (.A(cur_st[1]), .B(cur_st[0]), .Z(n6941)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i1_2_lut_rep_103.init = 16'heeee;
    LUT4 i4688_3_lut_rep_86_4_lut (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[2]), 
         .D(cur_st[3]), .Z(n6924)) /* synthesis lut_function=(A (C+(D))+!A ((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i4688_3_lut_rep_86_4_lut.init = 16'hfff1;
    LUT4 i26_4_lut_3_lut_4_lut (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[3]), 
         .D(cur_st[2]), .Z(spi_send_N_597)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C+(D))+!B (C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i26_4_lut_3_lut_4_lut.init = 16'h010e;
    LUT4 i1551_2_lut_4_lut_3_lut (.A(cur_st[0]), .B(cur_st[2]), .C(cur_st[3]), 
         .Z(n3463)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(50[14] 52[29])
    defparam i1551_2_lut_4_lut_3_lut.init = 16'h0202;
    LUT4 equal_205_i6_2_lut_rep_104 (.A(cur_st[2]), .B(cur_st[3]), .Z(n6942)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(35[23:34])
    defparam equal_205_i6_2_lut_rep_104.init = 16'hdddd;
    LUT4 i1_3_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[0]), 
         .D(cur_st[1]), .Z(n6408)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(35[23:34])
    defparam i1_3_lut_4_lut.init = 16'h0200;
    LUT4 n2948_bdd_2_lut_3_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[0]), 
         .D(cur_st[1]), .Z(n6837)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(35[23:34])
    defparam n2948_bdd_2_lut_3_lut_4_lut.init = 16'h0002;
    LUT4 i1_2_lut_rep_88_3_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[1]), 
         .D(cur_st[0]), .Z(n6926)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(35[23:34])
    defparam i1_2_lut_rep_88_3_lut_4_lut.init = 16'hfdff;
    CCU2D add_170_7 (.A0(x_tmp[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(x_tmp[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n5922), 
          .COUT(n5923), .S0(n695[5]), .S1(n695[6]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(106[29:36])
    defparam add_170_7.INIT0 = 16'h5aaa;
    defparam add_170_7.INIT1 = 16'h5aaa;
    defparam add_170_7.INJECT1_0 = "NO";
    defparam add_170_7.INJECT1_1 = "NO";
    LUT4 mux_864_i2_3_lut (.A(x_tmp[5]), .B(n2426[1]), .C(cur_st[0]), 
         .Z(n2441[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_864_i2_3_lut.init = 16'hcaca;
    LUT4 i3_4_lut (.A(x_tmp[2]), .B(x_tmp[4]), .C(x_tmp[0]), .D(x_tmp[1]), 
         .Z(n6427)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(101[20:30])
    defparam i3_4_lut.init = 16'hfeff;
    LUT4 i3_4_lut_adj_49 (.A(x_tmp[6]), .B(x_tmp[5]), .C(x_tmp[3]), .D(x_tmp[7]), 
         .Z(n6363)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(101[20:30])
    defparam i3_4_lut_adj_49.init = 16'hfeff;
    LUT4 mux_856_i2_3_lut (.A(y_tmp[1]), .B(x_tmp[1]), .C(cur_st[1]), 
         .Z(n2426[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_856_i2_3_lut.init = 16'hcaca;
    CCU2D y_tmp_1108_add_4_9 (.A0(y_tmp[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5943), .S0(n37[7]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108_add_4_9.INIT0 = 16'hfaaa;
    defparam y_tmp_1108_add_4_9.INIT1 = 16'h0000;
    defparam y_tmp_1108_add_4_9.INJECT1_0 = "NO";
    defparam y_tmp_1108_add_4_9.INJECT1_1 = "NO";
    CCU2D add_170_5 (.A0(x_tmp[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(x_tmp[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n5921), 
          .COUT(n5922), .S0(n695[3]), .S1(n695[4]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(106[29:36])
    defparam add_170_5.INIT0 = 16'h5aaa;
    defparam add_170_5.INIT1 = 16'h5aaa;
    defparam add_170_5.INJECT1_0 = "NO";
    defparam add_170_5.INJECT1_1 = "NO";
    CCU2D y_tmp_1108_add_4_7 (.A0(y_tmp[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(y_tmp[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5942), .COUT(n5943), .S0(n37[5]), .S1(n37[6]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108_add_4_7.INIT0 = 16'hfaaa;
    defparam y_tmp_1108_add_4_7.INIT1 = 16'hfaaa;
    defparam y_tmp_1108_add_4_7.INJECT1_0 = "NO";
    defparam y_tmp_1108_add_4_7.INJECT1_1 = "NO";
    CCU2D add_170_9 (.A0(x_tmp[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n5923), 
          .S0(n695[7]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(106[29:36])
    defparam add_170_9.INIT0 = 16'h5aaa;
    defparam add_170_9.INIT1 = 16'h0000;
    defparam add_170_9.INJECT1_0 = "NO";
    defparam add_170_9.INJECT1_1 = "NO";
    CCU2D y_tmp_1108_add_4_5 (.A0(y_tmp[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(y_tmp[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5941), .COUT(n5942), .S0(n37[3]), .S1(n37[4]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108_add_4_5.INIT0 = 16'hfaaa;
    defparam y_tmp_1108_add_4_5.INIT1 = 16'hfaaa;
    defparam y_tmp_1108_add_4_5.INJECT1_0 = "NO";
    defparam y_tmp_1108_add_4_5.INJECT1_1 = "NO";
    CCU2D y_tmp_1108_add_4_3 (.A0(y_tmp[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(y_tmp[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5940), .COUT(n5941), .S0(n37[1]), .S1(n37[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(103[29:36])
    defparam y_tmp_1108_add_4_3.INIT0 = 16'hfaaa;
    defparam y_tmp_1108_add_4_3.INIT1 = 16'hfaaa;
    defparam y_tmp_1108_add_4_3.INJECT1_0 = "NO";
    defparam y_tmp_1108_add_4_3.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module spi_master
//

module spi_master (n2954, clk_c, clk_c_enable_93, sck_reg_c, GND_net, 
            \spi_data_out[0] , clk_c_enable_35, n3963, miso_c, miso_N_337, 
            n6904, spi_send, nxt_st_4__N_226, \spi_data_out_7__N_33[7] , 
            \set_pos_y[1] , \spi_data_out_7__N_33[6] , \spi_data_out_7__N_33[5] , 
            \spi_data_out_7__N_33[4] , \spi_data_out_7__N_33[3] , \spi_data_out_7__N_33[2] , 
            \spi_data_out_7__N_33[1] , dc_in_N_211, n6905, dc_c_0, sck_c) /* synthesis syn_module_defined=1 */ ;
    output [3:0]n2954;
    input clk_c;
    output clk_c_enable_93;
    output sck_reg_c;
    input GND_net;
    input \spi_data_out[0] ;
    input clk_c_enable_35;
    input n3963;
    output miso_c;
    output miso_N_337;
    output n6904;
    input spi_send;
    output nxt_st_4__N_226;
    input \spi_data_out_7__N_33[7] ;
    input \set_pos_y[1] ;
    input \spi_data_out_7__N_33[6] ;
    input \spi_data_out_7__N_33[5] ;
    input \spi_data_out_7__N_33[4] ;
    input \spi_data_out_7__N_33[3] ;
    input \spi_data_out_7__N_33[2] ;
    input \spi_data_out_7__N_33[1] ;
    input dc_in_N_211;
    input n6905;
    output dc_c_0;
    output sck_c;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    wire sck_reg_c /* synthesis is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(31[12:19])
    wire sck_reg_N_250 /* synthesis is_inv_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(28[14:22])
    
    wire n996, sck_reg_N_252, n5955;
    wire [31:0]delay_count;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(30[14:25])
    wire [31:0]n133;
    
    wire n5956;
    wire [7:0]reg_data;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(28[14:22])
    
    wire sck_reg_N_250_enable_1;
    wire [3:0]count;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(21[13:18])
    wire [3:0]n21;
    
    wire n5954, n5953, cs;
    wire [3:0]n2954_c;
    
    wire miso_N_341, n5952, n3347, n5951, n5950, n5949, n5948, 
        n7, n55, n53, n54, n5, n52, n44, n48, n36, n50, 
        n40, n46, n32, sck_reg_N_250_enable_8;
    wire [7:0]reg_data_7__N_325;
    
    wire n992, n3349, n5963, n5962, n5961, n5960, n5959, n5958, 
        n5957;
    
    FD1P3AX cur_st_FSM_i0_i0 (.D(n996), .SP(clk_c_enable_93), .CK(clk_c), 
            .Q(n2954[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam cur_st_FSM_i0_i0.GSR = "DISABLED";
    FD1S3AX sck_reg_66 (.D(sck_reg_N_252), .CK(clk_c), .Q(sck_reg_c)) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(38[10] 42[25])
    defparam sck_reg_66.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_17 (.A0(delay_count[15]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[16]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5955), .COUT(n5956), .S0(n133[15]), 
          .S1(n133[16]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_17.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_17.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_17.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_17.INJECT1_1 = "NO";
    FD1P3AX reg_data_i0 (.D(\spi_data_out[0] ), .SP(sck_reg_N_250_enable_1), 
            .CK(sck_reg_N_250), .Q(reg_data[0])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i0.GSR = "DISABLED";
    FD1P3IX count_1105__i2 (.D(n21[2]), .SP(clk_c_enable_35), .CD(n3963), 
            .CK(clk_c), .Q(count[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam count_1105__i2.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_15 (.A0(delay_count[13]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[14]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5954), .COUT(n5955), .S0(n133[13]), 
          .S1(n133[14]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_15.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_15.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_15.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_15.INJECT1_1 = "NO";
    FD1P3IX count_1105__i1 (.D(n21[1]), .SP(clk_c_enable_35), .CD(n3963), 
            .CK(clk_c), .Q(count[1]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam count_1105__i1.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_13 (.A0(delay_count[11]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[12]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5953), .COUT(n5954), .S0(n133[11]), 
          .S1(n133[12]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_13.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_13.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_13.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_13.INJECT1_1 = "NO";
    FD1S3IX cs_68 (.D(miso_N_341), .CK(sck_reg_c), .CD(n2954_c[2]), .Q(cs)) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(74[10] 78[16])
    defparam cs_68.GSR = "DISABLED";
    FD1P3AX miso_70 (.D(reg_data[7]), .SP(miso_N_337), .CK(sck_reg_N_250), 
            .Q(miso_c)) /* synthesis lse_init_val=0, LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam miso_70.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_11 (.A0(delay_count[9]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[10]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5952), .COUT(n5953), .S0(n133[9]), 
          .S1(n133[10]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_11.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_11.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_11.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_11.INJECT1_1 = "NO";
    FD1P3IX count_1105__i3 (.D(n21[3]), .SP(clk_c_enable_35), .CD(n3963), 
            .CK(clk_c), .Q(count[3]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam count_1105__i3.GSR = "DISABLED";
    FD1P3AX cur_st_FSM_i0_i1 (.D(n3347), .SP(clk_c_enable_93), .CK(clk_c), 
            .Q(miso_N_337));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam cur_st_FSM_i0_i1.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_9 (.A0(delay_count[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(delay_count[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5951), .COUT(n5952), .S0(n133[7]), .S1(n133[8]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_9.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_9.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_9.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_9.INJECT1_1 = "NO";
    FD1P3IX count_1105__i0 (.D(n21[0]), .SP(clk_c_enable_35), .CD(n3963), 
            .CK(clk_c), .Q(count[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam count_1105__i0.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i0 (.D(n133[0]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i0.GSR = "DISABLED";
    CCU2D delay_count_1104_add_4_7 (.A0(delay_count[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(delay_count[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5950), .COUT(n5951), .S0(n133[5]), .S1(n133[6]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_7.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_7.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_7.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_7.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_5 (.A0(delay_count[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(delay_count[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5949), .COUT(n5950), .S0(n133[3]), .S1(n133[4]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_5.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_5.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_5.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_5.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_3 (.A0(delay_count[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(delay_count[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5948), .COUT(n5949), .S0(n133[1]), .S1(n133[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_3.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_3.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_3.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_3.INJECT1_1 = "NO";
    LUT4 i283_2_lut (.A(n7), .B(miso_N_337), .Z(n996)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam i283_2_lut.init = 16'h4444;
    LUT4 i3993_1_lut (.A(count[0]), .Z(n21[0])) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam i3993_1_lut.init = 16'h5555;
    LUT4 i1_4_lut (.A(n55), .B(delay_count[5]), .C(n53), .D(n54), .Z(n5)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
    defparam i1_4_lut.init = 16'hfffb;
    CCU2D delay_count_1104_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(delay_count[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n5948), .S1(n133[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_1.INIT0 = 16'hF000;
    defparam delay_count_1104_add_4_1.INIT1 = 16'h0555;
    defparam delay_count_1104_add_4_1.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_1.INJECT1_1 = "NO";
    LUT4 i26_4_lut (.A(delay_count[14]), .B(n52), .C(n44), .D(delay_count[6]), 
         .Z(n55)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i26_4_lut.init = 16'hfffe;
    LUT4 i24_4_lut (.A(delay_count[20]), .B(n48), .C(n36), .D(delay_count[8]), 
         .Z(n53)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i24_4_lut.init = 16'hfffe;
    LUT4 i25_4_lut (.A(delay_count[25]), .B(n50), .C(n40), .D(delay_count[9]), 
         .Z(n54)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i25_4_lut.init = 16'hfffe;
    LUT4 i23_4_lut (.A(delay_count[24]), .B(n46), .C(n32), .D(delay_count[0]), 
         .Z(n52)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i23_4_lut.init = 16'hfffe;
    LUT4 i15_3_lut (.A(delay_count[15]), .B(delay_count[31]), .C(delay_count[3]), 
         .Z(n44)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i15_3_lut.init = 16'hfefe;
    LUT4 i17_4_lut (.A(delay_count[26]), .B(delay_count[12]), .C(delay_count[28]), 
         .D(delay_count[18]), .Z(n46)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i17_4_lut.init = 16'hfffe;
    LUT4 i3_2_lut (.A(delay_count[13]), .B(delay_count[22]), .Z(n32)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i3_2_lut.init = 16'heeee;
    LUT4 i19_4_lut (.A(delay_count[7]), .B(delay_count[19]), .C(delay_count[11]), 
         .D(delay_count[21]), .Z(n48)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i19_4_lut.init = 16'hfffe;
    FD1P3AX reg_data_i7 (.D(reg_data_7__N_325[7]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[7])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i7.GSR = "DISABLED";
    FD1P3AX reg_data_i6 (.D(reg_data_7__N_325[6]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[6])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i6.GSR = "DISABLED";
    FD1P3AX reg_data_i5 (.D(reg_data_7__N_325[5]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[5])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i5.GSR = "DISABLED";
    FD1P3AX reg_data_i4 (.D(reg_data_7__N_325[4]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[4])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i4.GSR = "DISABLED";
    FD1P3AX reg_data_i3 (.D(reg_data_7__N_325[3]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[3])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i3.GSR = "DISABLED";
    FD1P3AX reg_data_i2 (.D(reg_data_7__N_325[2]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i2.GSR = "DISABLED";
    FD1P3AX reg_data_i1 (.D(reg_data_7__N_325[1]), .SP(sck_reg_N_250_enable_8), 
            .CK(sck_reg_N_250), .Q(reg_data[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=16, LSE_RCOL=6, LSE_LLINE=65, LSE_RLINE=79 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(92[10] 98[33])
    defparam reg_data_i1.GSR = "DISABLED";
    FD1P3AX cur_st_FSM_i0_i2 (.D(n992), .SP(clk_c_enable_93), .CK(clk_c), 
            .Q(n2954_c[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam cur_st_FSM_i0_i2.GSR = "DISABLED";
    LUT4 i7_2_lut (.A(delay_count[16]), .B(delay_count[29]), .Z(n36)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i7_2_lut.init = 16'heeee;
    LUT4 i1409_2_lut (.A(spi_send), .B(miso_N_337), .Z(sck_reg_N_250_enable_1)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam i1409_2_lut.init = 16'h2222;
    LUT4 i21_4_lut (.A(delay_count[2]), .B(delay_count[27]), .C(delay_count[23]), 
         .D(delay_count[30]), .Z(n50)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i21_4_lut.init = 16'hfffe;
    LUT4 i11_2_lut (.A(delay_count[10]), .B(delay_count[17]), .Z(n40)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i11_2_lut.init = 16'heeee;
    LUT4 i2_4_lut (.A(count[1]), .B(count[0]), .C(count[2]), .D(count[3]), 
         .Z(n7)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
    defparam i2_4_lut.init = 16'hff7f;
    FD1P3AX cur_st_FSM_i0_i3 (.D(n3349), .SP(clk_c_enable_93), .CK(clk_c), 
            .Q(nxt_st_4__N_226));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam cur_st_FSM_i0_i3.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i1 (.D(n133[1]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i1.GSR = "DISABLED";
    LUT4 i4661_3_lut_rep_66 (.A(n5), .B(delay_count[4]), .C(delay_count[1]), 
         .Z(n6904)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i4661_3_lut_rep_66.init = 16'h4040;
    FD1S3IX delay_count_1104__i2 (.D(n133[2]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i2.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i3 (.D(n133[3]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i3.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i4 (.D(n133[4]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i4.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i5 (.D(n133[5]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i5.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i6 (.D(n133[6]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i6.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i7 (.D(n133[7]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i7.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i8 (.D(n133[8]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i8.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i9 (.D(n133[9]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i9.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i10 (.D(n133[10]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i10.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i11 (.D(n133[11]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i11.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i12 (.D(n133[12]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i12.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i13 (.D(n133[13]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i13.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i14 (.D(n133[14]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i14.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i15 (.D(n133[15]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i15.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i16 (.D(n133[16]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i16.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i17 (.D(n133[17]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i17.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i18 (.D(n133[18]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i18.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i19 (.D(n133[19]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i19.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i20 (.D(n133[20]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i20.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i21 (.D(n133[21]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i21.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i22 (.D(n133[22]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i22.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i23 (.D(n133[23]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i23.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i24 (.D(n133[24]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i24.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i25 (.D(n133[25]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i25.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i26 (.D(n133[26]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i26.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i27 (.D(n133[27]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i27.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i28 (.D(n133[28]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i28.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i29 (.D(n133[29]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i29.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i30 (.D(n133[30]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i30.GSR = "DISABLED";
    FD1S3IX delay_count_1104__i31 (.D(n133[31]), .CK(clk_c), .CD(n6904), 
            .Q(delay_count[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104__i31.GSR = "DISABLED";
    LUT4 i4673_2_lut_rep_62_4_lut (.A(n5), .B(delay_count[4]), .C(delay_count[1]), 
         .D(sck_reg_c), .Z(clk_c_enable_93)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i4673_2_lut_rep_62_4_lut.init = 16'h0040;
    LUT4 i3995_2_lut (.A(count[1]), .B(count[0]), .Z(n21[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam i3995_2_lut.init = 16'h6666;
    LUT4 i1_2_lut_4_lut (.A(n5), .B(delay_count[4]), .C(delay_count[1]), 
         .D(sck_reg_c), .Z(sck_reg_N_252)) /* synthesis lut_function=(A (D)+!A !(B (C (D)+!C !(D))+!B !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(41[12:27])
    defparam i1_2_lut_4_lut.init = 16'hbf40;
    LUT4 i1_2_lut (.A(spi_send), .B(miso_N_337), .Z(sck_reg_N_250_enable_8)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut.init = 16'heeee;
    LUT4 mux_59_i8_4_lut (.A(\spi_data_out_7__N_33[7] ), .B(reg_data[6]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[7])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i8_4_lut.init = 16'hcac0;
    LUT4 mux_59_i7_4_lut (.A(\spi_data_out_7__N_33[6] ), .B(reg_data[5]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[6])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i7_4_lut.init = 16'hcac0;
    LUT4 mux_59_i6_4_lut (.A(\spi_data_out_7__N_33[5] ), .B(reg_data[4]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[5])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i6_4_lut.init = 16'hcac0;
    LUT4 mux_59_i5_4_lut (.A(\spi_data_out_7__N_33[4] ), .B(reg_data[3]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[4])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i5_4_lut.init = 16'hcac0;
    LUT4 i1435_3_lut (.A(miso_N_337), .B(n2954_c[2]), .C(n7), .Z(n3347)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam i1435_3_lut.init = 16'hecec;
    LUT4 mux_59_i4_4_lut (.A(\spi_data_out_7__N_33[3] ), .B(reg_data[2]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[3])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i4_4_lut.init = 16'hcac0;
    LUT4 mux_59_i3_4_lut (.A(\spi_data_out_7__N_33[2] ), .B(reg_data[1]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[2])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i3_4_lut.init = 16'hcac0;
    LUT4 mux_59_i2_4_lut (.A(\spi_data_out_7__N_33[1] ), .B(reg_data[0]), 
         .C(miso_N_337), .D(\set_pos_y[1] ), .Z(reg_data_7__N_325[1])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(97[12] 98[33])
    defparam mux_59_i2_4_lut.init = 16'hcac0;
    LUT4 i279_2_lut (.A(spi_send), .B(nxt_st_4__N_226), .Z(n992)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam i279_2_lut.init = 16'h8888;
    LUT4 i1437_3_lut (.A(nxt_st_4__N_226), .B(n2954[0]), .C(spi_send), 
         .Z(n3349)) /* synthesis lut_function=(A (B+!(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(58[5] 64[12])
    defparam i1437_3_lut.init = 16'hcece;
    LUT4 miso_N_337_I_0_1_lut (.A(miso_N_337), .Z(miso_N_341)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(78[10:16])
    defparam miso_N_337_I_0_1_lut.init = 16'h5555;
    CCU2D delay_count_1104_add_4_33 (.A0(delay_count[31]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n5963), .S0(n133[31]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_33.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_33.INIT1 = 16'h0000;
    defparam delay_count_1104_add_4_33.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_33.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_31 (.A0(delay_count[29]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[30]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5962), .COUT(n5963), .S0(n133[29]), 
          .S1(n133[30]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_31.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_31.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_31.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_31.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_29 (.A0(delay_count[27]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[28]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5961), .COUT(n5962), .S0(n133[27]), 
          .S1(n133[28]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_29.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_29.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_29.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_29.INJECT1_1 = "NO";
    LUT4 i4002_2_lut_3_lut (.A(count[1]), .B(count[0]), .C(count[2]), 
         .Z(n21[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam i4002_2_lut_3_lut.init = 16'h7878;
    LUT4 i4009_3_lut_4_lut (.A(count[1]), .B(count[0]), .C(count[2]), 
         .D(count[3]), .Z(n21[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(85[13:20])
    defparam i4009_3_lut_4_lut.init = 16'h7f80;
    CCU2D delay_count_1104_add_4_27 (.A0(delay_count[25]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[26]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5960), .COUT(n5961), .S0(n133[25]), 
          .S1(n133[26]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_27.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_27.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_27.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_27.INJECT1_1 = "NO";
    LUT4 i2_4_lut_adj_48 (.A(dc_in_N_211), .B(n6905), .C(cs), .D(\set_pos_y[1] ), 
         .Z(dc_c_0)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i2_4_lut_adj_48.init = 16'h0800;
    LUT4 i2_3_lut (.A(n2954[0]), .B(sck_reg_c), .C(cs), .Z(sck_c)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(46[7] 48[13])
    defparam i2_3_lut.init = 16'hfefe;
    CCU2D delay_count_1104_add_4_25 (.A0(delay_count[23]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[24]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5959), .COUT(n5960), .S0(n133[23]), 
          .S1(n133[24]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_25.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_25.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_25.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_25.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_23 (.A0(delay_count[21]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[22]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5958), .COUT(n5959), .S0(n133[21]), 
          .S1(n133[22]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_23.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_23.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_23.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_23.INJECT1_1 = "NO";
    INV i4862 (.A(sck_reg_c), .Z(sck_reg_N_250));
    CCU2D delay_count_1104_add_4_21 (.A0(delay_count[19]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[20]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5957), .COUT(n5958), .S0(n133[19]), 
          .S1(n133[20]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_21.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_21.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_21.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_21.INJECT1_1 = "NO";
    CCU2D delay_count_1104_add_4_19 (.A0(delay_count[17]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(delay_count[18]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n5956), .COUT(n5957), .S0(n133[17]), 
          .S1(n133[18]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/spi_master.v(36[22:35])
    defparam delay_count_1104_add_4_19.INIT0 = 16'hfaaa;
    defparam delay_count_1104_add_4_19.INIT1 = 16'hfaaa;
    defparam delay_count_1104_add_4_19.INJECT1_0 = "NO";
    defparam delay_count_1104_add_4_19.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module oled_init
//

module oled_init (n2961, clk_c, clk_c_enable_14, n7234, n6922, spi_data_7__N_350, 
            \spi_data_init[7] , spi_data_7__N_348, n6956, n3497, spi_data_7__N_346, 
            n6957, \spi_data_init[4] , \spi_data_init[6] , clk_c_enable_62, 
            n7233, spi_data_7__N_352, spi_data_7__N_354, spi_data_7__N_355, 
            \spi_data_init[1] , n6936, n6937, \cur_st[0] , \cur_st[2] , 
            n6408, n41, \spi_data_init[0] , \spi_data_init[3] , \spi_data_init[5] ) /* synthesis syn_module_defined=1 */ ;
    output [11:0]n2961;
    input clk_c;
    input clk_c_enable_14;
    input n7234;
    output n6922;
    output spi_data_7__N_350;
    output \spi_data_init[7] ;
    output spi_data_7__N_348;
    output n6956;
    output n3497;
    output spi_data_7__N_346;
    output n6957;
    output \spi_data_init[4] ;
    output \spi_data_init[6] ;
    input clk_c_enable_62;
    input n7233;
    output spi_data_7__N_352;
    output spi_data_7__N_354;
    output spi_data_7__N_355;
    output \spi_data_init[1] ;
    output n6936;
    output n6937;
    input \cur_st[0] ;
    input \cur_st[2] ;
    input n6408;
    output n41;
    output \spi_data_init[0] ;
    output \spi_data_init[3] ;
    output \spi_data_init[5] ;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    
    wire n6923, n3481;
    wire [11:0]n2961_c;
    wire [7:0]n2736;
    
    wire n6961, n6962, n6963, n4, n3334, n6914, n3489, n3486, 
        n3303, n6938, n3606, n6927;
    
    FD1P3AX cur_st_FSM_i0_i0 (.D(n7234), .SP(clk_c_enable_14), .CK(clk_c), 
            .Q(n2961[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i0.GSR = "ENABLED";
    LUT4 mux_941_i3_4_lut (.A(n6923), .B(n3481), .C(n6922), .D(n2961_c[7]), 
         .Z(n2736[2])) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_941_i3_4_lut.init = 16'hfaca;
    LUT4 i1569_2_lut (.A(spi_data_7__N_350), .B(n2961_c[5]), .Z(n3481)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam i1569_2_lut.init = 16'h4444;
    PFUMX i4762 (.BLUT(n6961), .ALUT(n6962), .C0(n2961_c[3]), .Z(n6963));
    LUT4 i1422_4_lut_4_lut_4_lut (.A(n2961_c[7]), .B(n4), .C(spi_data_7__N_350), 
         .D(n2961_c[3]), .Z(n3334)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam i1422_4_lut_4_lut_4_lut.init = 16'h5554;
    LUT4 i3374_4_lut_4_lut_4_lut (.A(n2961_c[7]), .B(spi_data_7__N_350), 
         .C(n6914), .D(n3489), .Z(\spi_data_init[7] )) /* synthesis lut_function=(A (C)+!A (B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam i3374_4_lut_4_lut_4_lut.init = 16'hf5f4;
    LUT4 i4694_2_lut_rep_118 (.A(n2961_c[9]), .B(spi_data_7__N_348), .Z(n6956)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i4694_2_lut_rep_118.init = 16'h1111;
    LUT4 i1585_3_lut_3_lut (.A(n2961_c[9]), .B(spi_data_7__N_348), .C(n2736[2]), 
         .Z(n3497)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;
    defparam i1585_3_lut_3_lut.init = 16'h5454;
    LUT4 i935_2_lut_rep_119 (.A(spi_data_7__N_346), .B(n2961_c[11]), .Z(n6957)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i935_2_lut_rep_119.init = 16'heeee;
    LUT4 i1584_4_lut_4_lut_4_lut (.A(spi_data_7__N_346), .B(n2961_c[11]), 
         .C(n6963), .D(n6956), .Z(\spi_data_init[4] )) /* synthesis lut_function=(!(A (B)+!A (B+!(C (D))))) */ ;
    defparam i1584_4_lut_4_lut_4_lut.init = 16'h3222;
    LUT4 i941_2_lut_rep_76_2_lut_3_lut_4_lut (.A(spi_data_7__N_346), .B(n2961_c[11]), 
         .C(spi_data_7__N_348), .D(n2961_c[9]), .Z(n6914)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i941_2_lut_rep_76_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1582_4_lut_4_lut_4_lut (.A(spi_data_7__N_346), .B(n2961_c[11]), 
         .C(n2736[6]), .D(n6956), .Z(\spi_data_init[6] )) /* synthesis lut_function=(!(A (B)+!A (B+!(C (D))))) */ ;
    defparam i1582_4_lut_4_lut_4_lut.init = 16'h3222;
    LUT4 i1574_3_lut (.A(spi_data_7__N_346), .B(n2961_c[11]), .C(n2961_c[9]), 
         .Z(n3486)) /* synthesis lut_function=(A (B)+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam i1574_3_lut.init = 16'hcdcd;
    LUT4 i1391_3_lut (.A(spi_data_7__N_346), .B(n2961_c[11]), .C(n2961_c[9]), 
         .Z(n3303)) /* synthesis lut_function=(!(A (B)+!A (B+(C)))) */ ;
    defparam i1391_3_lut.init = 16'h2323;
    FD1P3AY cur_st_FSM_i0_i11 (.D(n7233), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(n2961_c[11]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i11.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i10 (.D(n2961_c[11]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(spi_data_7__N_346));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i10.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i9 (.D(spi_data_7__N_346), .SP(clk_c_enable_62), 
            .CK(clk_c), .Q(n2961_c[9]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i9.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i8 (.D(n2961_c[9]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(spi_data_7__N_348));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i8.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i7 (.D(spi_data_7__N_348), .SP(clk_c_enable_62), 
            .CK(clk_c), .Q(n2961_c[7]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i7.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i6 (.D(n2961_c[7]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(spi_data_7__N_350));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i6.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i5 (.D(spi_data_7__N_350), .SP(clk_c_enable_62), 
            .CK(clk_c), .Q(n2961_c[5]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i5.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i4 (.D(n2961_c[5]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(spi_data_7__N_352));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i4.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i3 (.D(spi_data_7__N_352), .SP(clk_c_enable_62), 
            .CK(clk_c), .Q(n2961_c[3]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i3.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i2 (.D(n2961_c[3]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(spi_data_7__N_354));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i2.GSR = "ENABLED";
    FD1P3AX cur_st_FSM_i0_i1 (.D(spi_data_7__N_354), .SP(clk_c_enable_62), 
            .CK(clk_c), .Q(spi_data_7__N_355));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam cur_st_FSM_i0_i1.GSR = "ENABLED";
    LUT4 mux_943_i2_4_lut_4_lut (.A(n6938), .B(n6914), .C(n2961_c[11]), 
         .D(n3606), .Z(\spi_data_init[1] )) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_943_i2_4_lut_4_lut.init = 16'hd1c0;
    LUT4 i1694_3_lut_4_lut (.A(spi_data_7__N_355), .B(n6936), .C(n2961_c[5]), 
         .D(spi_data_7__N_352), .Z(n3606)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam i1694_3_lut_4_lut.init = 16'hf0f2;
    LUT4 mux_941_i4_3_lut_4_lut_3_lut_4_lut (.A(spi_data_7__N_355), .B(n6936), 
         .C(n6937), .D(n6938), .Z(n2736[3])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B (D))+!A ((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_941_i4_3_lut_4_lut_3_lut_4_lut.init = 16'h00f2;
    LUT4 i1_3_lut (.A(\cur_st[0] ), .B(\cur_st[2] ), .C(n6408), .Z(n41)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_clear.v(45[14:20])
    defparam i1_3_lut.init = 16'hecec;
    LUT4 i4600_3_lut_4_lut_4_lut (.A(n6956), .B(n3334), .C(n3303), .D(n6957), 
         .Z(\spi_data_init[0] )) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C)) */ ;
    defparam i4600_3_lut_4_lut_4_lut.init = 16'hf0d8;
    LUT4 i4598_3_lut_4_lut_4_lut (.A(n6956), .B(n2736[3]), .C(n3486), 
         .D(n6957), .Z(\spi_data_init[3] )) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C)) */ ;
    defparam i4598_3_lut_4_lut_4_lut.init = 16'hf0d8;
    LUT4 mux_941_i5_4_lut_then_3_lut (.A(n2961_c[5]), .B(spi_data_7__N_350), 
         .C(n2961_c[7]), .Z(n6962)) /* synthesis lut_function=(A (C)+!A ((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_941_i5_4_lut_then_3_lut.init = 16'hf1f1;
    LUT4 mux_941_i5_4_lut_else_3_lut (.A(n2961_c[5]), .B(spi_data_7__N_350), 
         .C(n2961_c[7]), .D(spi_data_7__N_352), .Z(n6961)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_941_i5_4_lut_else_3_lut.init = 16'hf1f0;
    LUT4 mux_943_i6_4_lut (.A(n6927), .B(n2961_c[11]), .C(n6914), .D(n6922), 
         .Z(\spi_data_init[5] )) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(64[9] 78[16])
    defparam mux_943_i6_4_lut.init = 16'hc0ca;
    LUT4 i134_2_lut_rep_98 (.A(n2961_c[3]), .B(spi_data_7__N_354), .Z(n6936)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(26[21:29])
    defparam i134_2_lut_rep_98.init = 16'heeee;
    LUT4 i1_2_lut_rep_85_3_lut (.A(n2961_c[3]), .B(spi_data_7__N_354), .C(spi_data_7__N_355), 
         .Z(n6923)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(26[21:29])
    defparam i1_2_lut_rep_85_3_lut.init = 16'h1010;
    LUT4 i1_2_lut_rep_89_3_lut (.A(n2961_c[3]), .B(spi_data_7__N_354), .C(spi_data_7__N_355), 
         .Z(n6927)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(26[21:29])
    defparam i1_2_lut_rep_89_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_3_lut_4_lut (.A(n2961_c[3]), .B(spi_data_7__N_354), .C(n6937), 
         .D(spi_data_7__N_355), .Z(n3489)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled.v(26[21:29])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i929_2_lut_rep_99 (.A(spi_data_7__N_352), .B(n2961_c[5]), .Z(n6937)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i929_2_lut_rep_99.init = 16'heeee;
    LUT4 mux_941_i7_3_lut_4_lut_3_lut_4_lut (.A(spi_data_7__N_352), .B(n2961_c[5]), 
         .C(n2961_c[3]), .D(n6938), .Z(n2736[6])) /* synthesis lut_function=(!(A (D)+!A (B (D)+!B ((D)+!C)))) */ ;
    defparam mux_941_i7_3_lut_4_lut_3_lut_4_lut.init = 16'h00fe;
    LUT4 i1_3_lut_4_lut (.A(spi_data_7__N_352), .B(n2961_c[5]), .C(spi_data_7__N_354), 
         .D(spi_data_7__N_355), .Z(n4)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;
    defparam i1_3_lut_4_lut.init = 16'hefee;
    LUT4 i1_2_lut_rep_100 (.A(n2961_c[7]), .B(spi_data_7__N_350), .Z(n6938)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_100.init = 16'heeee;
    LUT4 i3_2_lut_rep_84_3_lut_4_lut (.A(n2961_c[7]), .B(spi_data_7__N_350), 
         .C(n2961_c[5]), .D(spi_data_7__N_352), .Z(n6922)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3_2_lut_rep_84_3_lut_4_lut.init = 16'hfffe;
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module oled_write_data
//

module oled_write_data (clk_c, \set_pos_y[1] , spi_data_write, \cur_st[0]_derived_8 , 
            cur_st, clk_c_enable_64, \nxt_st[0] , spi_send_write, \write_data_tmp[29] , 
            n7233, n6901, n3646, n6913, n3291, n4, n6899, n6933, 
            \nxt_st[2] , \nxt_st[1] , n6810, n6912, \write_data_tmp_47__N_406[38] , 
            \write_data_tmp_47__N_406[37] , \write_data_tmp_47__N_406[32] , 
            \write_data_tmp[30] , \write_data_tmp[24] , n6893, n3299, 
            n6894, n6928, sck_N_335, n6510, GND_net, n6954, n5988, 
            \cur_st[0] , n6460, sck_reg_c, n6904, n6403, \nxt_st_3__N_472[0] , 
            \nxt_st_3__N_468[2] , n6932, n6951, \cur_st[2] , n6929, 
            n5266, n6402, spi_send_N_200, \nxt_st_3__N_468[1] , write_start, 
            n6908, n5247, n3597) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    input \set_pos_y[1] ;
    output [7:0]spi_data_write;
    input \cur_st[0]_derived_8 ;
    output [3:0]cur_st;
    input clk_c_enable_64;
    input \nxt_st[0] ;
    output spi_send_write;
    output \write_data_tmp[29] ;
    input n7233;
    input n6901;
    output n3646;
    output n6913;
    input n3291;
    input n4;
    input n6899;
    output n6933;
    input \nxt_st[2] ;
    input \nxt_st[1] ;
    input n6810;
    input n6912;
    input \write_data_tmp_47__N_406[38] ;
    input \write_data_tmp_47__N_406[37] ;
    input \write_data_tmp_47__N_406[32] ;
    output \write_data_tmp[30] ;
    output \write_data_tmp[24] ;
    input n6893;
    input n3299;
    input n6894;
    output n6928;
    input sck_N_335;
    output n6510;
    input GND_net;
    input n6954;
    output n5988;
    input \cur_st[0] ;
    output n6460;
    input sck_reg_c;
    input n6904;
    input n6403;
    output \nxt_st_3__N_472[0] ;
    output \nxt_st_3__N_468[2] ;
    input n6932;
    input n6951;
    input \cur_st[2] ;
    output n6929;
    input n5266;
    input n6402;
    input spi_send_N_200;
    output \nxt_st_3__N_468[1] ;
    input write_start;
    output n6908;
    input n5247;
    output n3597;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(29[11:14])
    wire spi_send_N_504 /* synthesis is_clock=1, SET_AS_NETWORK=\oled_write_data/spi_send_N_504 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(25[16:24])
    wire sck_reg_c /* synthesis is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_top.v(31[12:19])
    wire [7:0]x_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(41[14:19])
    
    wire clk_c_enable_96;
    wire [7:0]n47;
    wire [3:0]count;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(47[14:19])
    
    wire clk_c_enable_87;
    wire [3:0]n21;
    wire [7:0]y_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(41[20:25])
    
    wire clk_c_enable_7;
    wire [47:0]write_data_tmp;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(46[15:29])
    
    wire n6915;
    wire [7:0]n1856;
    
    wire spi_send_N_503;
    wire [7:0]n37;
    
    wire n6947, n6396, n6960, n3956, n3524;
    wire [31:0]nxt_st_3__N_468;
    
    wire n6000;
    wire [47:0]write_data_tmp_47__N_406;
    
    wire n6920;
    wire [28:0]n3272;
    
    wire n6976;
    wire [7:0]n1897;
    
    wire n6946, n2, n5947, n5946, n5945, n6959, n5944, n6958, 
        n2_adj_602, n2_adj_603, n2_adj_604;
    
    FD1P3AX x_tmp_1106__i3 (.D(n47[3]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i3.GSR = "ENABLED";
    FD1P3AX x_tmp_1106__i2 (.D(n47[2]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i2.GSR = "ENABLED";
    FD1P3AX x_tmp_1106__i1 (.D(n47[1]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i1.GSR = "ENABLED";
    FD1P3IX count_1107__i1 (.D(n21[1]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(count[1]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam count_1107__i1.GSR = "ENABLED";
    FD1P3AX y_tmp__i1 (.D(\set_pos_y[1] ), .SP(clk_c_enable_7), .CK(clk_c), 
            .Q(y_tmp[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam y_tmp__i1.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i43 (.D(write_data_tmp[35]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[43])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i43.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i1 (.D(n1856[0]), .CK(\cur_st[0]_derived_8 ), 
           .CD(n6915), .Q(spi_data_write[0])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i1.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i40 (.D(write_data_tmp[32]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[40])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i40.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i44 (.D(write_data_tmp[36]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[44])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i44.GSR = "ENABLED";
    FD1P3AX cur_st_i0_i0 (.D(\nxt_st[0] ), .SP(clk_c_enable_64), .CK(clk_c), 
            .Q(cur_st[0])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(53[14] 55[29])
    defparam cur_st_i0_i0.GSR = "ENABLED";
    FD1S1A spi_send_I_0 (.D(spi_send_N_503), .CK(spi_send_N_504), .Q(spi_send_write)) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_send_I_0.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i11 (.D(write_data_tmp[2]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[11])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i11.GSR = "ENABLED";
    FD1P3IX x_tmp_1106__i7 (.D(n37[7]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(x_tmp[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i7.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i41 (.D(write_data_tmp[37]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[41])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i41.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i2 (.D(n1856[1]), .CK(\cur_st[0]_derived_8 ), 
           .CD(n6915), .Q(spi_data_write[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i2.GSR = "ENABLED";
    LUT4 equal_819_i3_2_lut_rep_109 (.A(cur_st[2]), .B(cur_st[3]), .Z(n6947)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(81[13:14])
    defparam equal_819_i3_2_lut_rep_109.init = 16'heeee;
    LUT4 i1_2_lut_3_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[1]), 
         .Z(n6396)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(81[13:14])
    defparam i1_2_lut_3_lut.init = 16'h1010;
    FD1S1I spi_data_7__I_0_i3 (.D(n1856[2]), .CK(\cur_st[0]_derived_8 ), 
           .CD(n6915), .Q(spi_data_write[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i3.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i4 (.D(n1856[3]), .CK(\cur_st[0]_derived_8 ), 
           .CD(n6915), .Q(spi_data_write[3])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i4.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i5 (.D(n1856[4]), .CK(\cur_st[0]_derived_8 ), 
           .CD(n6915), .Q(spi_data_write[4])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i5.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i6 (.D(n6960), .CK(\cur_st[0]_derived_8 ), .CD(n6915), 
           .Q(spi_data_write[5])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i6.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i9 (.D(write_data_tmp[1]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[9])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i9.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i42 (.D(write_data_tmp[34]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[42])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i42.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i29 (.D(write_data_tmp[21]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(\write_data_tmp[29] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i29.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i27 (.D(write_data_tmp[19]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[27])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i27.GSR = "ENABLED";
    FD1P3AX cur_st_i0_i3 (.D(n7233), .SP(clk_c_enable_64), .CK(clk_c), 
            .Q(cur_st[3])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(53[14] 55[29])
    defparam cur_st_i0_i3.GSR = "ENABLED";
    FD1P3IX write_data_tmp_i0_i46 (.D(write_data_tmp[38]), .SP(clk_c_enable_96), 
            .CD(clk_c_enable_87), .CK(clk_c), .Q(write_data_tmp[46])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i46.GSR = "ENABLED";
    FD1P3IX count_1107__i0 (.D(n21[0]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(count[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam count_1107__i0.GSR = "ENABLED";
    FD1P3IX x_tmp_1106__i0 (.D(n37[0]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(x_tmp[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i0.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i7 (.D(n3524), .CK(\cur_st[0]_derived_8 ), .CD(n3956), 
           .Q(spi_data_write[6])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i7.GSR = "ENABLED";
    FD1S1I spi_data_7__I_0_i8 (.D(n6000), .CK(\cur_st[0]_derived_8 ), .CD(nxt_st_3__N_468[0]), 
           .Q(spi_data_write[7])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(73[5] 86[20])
    defparam spi_data_7__I_0_i8.GSR = "ENABLED";
    LUT4 i4620_2_lut_rep_77_2_lut_3_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), 
         .C(cur_st[0]), .D(cur_st[1]), .Z(n6915)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(81[13:14])
    defparam i4620_2_lut_rep_77_2_lut_3_lut_4_lut.init = 16'h0001;
    LUT4 i4634_2_lut_2_lut_3_lut_3_lut_3_lut_4_lut_3_lut_4_lut (.A(cur_st[2]), 
         .B(cur_st[3]), .C(cur_st[1]), .D(cur_st[0]), .Z(n3524)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(81[13:14])
    defparam i4634_2_lut_2_lut_3_lut_3_lut_3_lut_4_lut_3_lut_4_lut.init = 16'h0002;
    LUT4 i1_3_lut_4_lut (.A(n6901), .B(n3646), .C(n6913), .D(write_data_tmp[26]), 
         .Z(write_data_tmp_47__N_406[34])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam i1_3_lut_4_lut.init = 16'h4f40;
    LUT4 mux_841_i31_3_lut_4_lut (.A(cur_st[1]), .B(n6920), .C(n3291), 
         .D(write_data_tmp[22]), .Z(write_data_tmp_47__N_406[30])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam mux_841_i31_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_841_i29_3_lut_4_lut (.A(cur_st[1]), .B(n6920), .C(n3272[8]), 
         .D(write_data_tmp[20]), .Z(write_data_tmp_47__N_406[28])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam mux_841_i29_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i4698_4_lut_4_lut_4_lut (.A(cur_st[0]), .B(cur_st[2]), .C(cur_st[3]), 
         .D(n4), .Z(clk_c_enable_96)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam i4698_4_lut_4_lut_4_lut.init = 16'h0009;
    LUT4 i1685_2_lut_3_lut_4_lut_4_lut_then_3_lut (.A(cur_st[1]), .B(cur_st[2]), 
         .C(cur_st[3]), .Z(spi_send_N_504)) /* synthesis lut_function=(!(A (B+(C))+!A (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(80[13:14])
    defparam i1685_2_lut_3_lut_4_lut_4_lut_then_3_lut.init = 16'h0707;
    LUT4 i1685_2_lut_3_lut_4_lut_4_lut_else_3_lut (.A(cur_st[1]), .B(cur_st[2]), 
         .C(cur_st[3]), .D(cur_st[0]), .Z(n6976)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C)+!B (C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(80[13:14])
    defparam i1685_2_lut_3_lut_4_lut_4_lut_else_3_lut.init = 16'h0706;
    LUT4 i3964_1_lut (.A(count[0]), .Z(n21[0])) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam i3964_1_lut.init = 16'h5555;
    LUT4 mux_841_i13_3_lut_4_lut (.A(n6899), .B(n3646), .C(n6913), .D(write_data_tmp[2]), 
         .Z(write_data_tmp_47__N_406[12])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i13_3_lut_4_lut.init = 16'h4f40;
    LUT4 i1536_2_lut_3_lut_4_lut (.A(cur_st[0]), .B(n6933), .C(clk_c_enable_96), 
         .D(cur_st[1]), .Z(clk_c_enable_87)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam i1536_2_lut_3_lut_4_lut.init = 16'hf0d0;
    LUT4 mux_841_i27_3_lut_4_lut (.A(n6899), .B(n3646), .C(n6913), .D(write_data_tmp[18]), 
         .Z(write_data_tmp_47__N_406[26])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i27_3_lut_4_lut.init = 16'h4f40;
    LUT4 i4636_3_lut_4_lut_4_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[0]), 
         .D(cur_st[1]), .Z(n6000)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(81[13:14])
    defparam i4636_3_lut_4_lut_4_lut_4_lut.init = 16'h0010;
    LUT4 i2_3_lut_4_lut (.A(cur_st[1]), .B(n6947), .C(\set_pos_y[1] ), 
         .D(cur_st[0]), .Z(n3646)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i2_3_lut_4_lut.init = 16'h0010;
    FD1P3AX cur_st_i0_i2 (.D(\nxt_st[2] ), .SP(clk_c_enable_64), .CK(clk_c), 
            .Q(cur_st[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(53[14] 55[29])
    defparam cur_st_i0_i2.GSR = "ENABLED";
    FD1P3AX cur_st_i0_i1 (.D(\nxt_st[1] ), .SP(clk_c_enable_64), .CK(clk_c), 
            .Q(cur_st[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(53[14] 55[29])
    defparam cur_st_i0_i1.GSR = "ENABLED";
    LUT4 x_tmp_1106_mux_6_i4_4_lut (.A(n37[3]), .B(n6810), .C(n6913), 
         .D(n3646), .Z(n47[3])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i4_4_lut.init = 16'h3a0a;
    LUT4 mux_841_i25_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[16]), 
         .Z(write_data_tmp_47__N_406[24])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i25_3_lut_4_lut.init = 16'h8f80;
    FD1P3AX write_data_tmp_i0_i38 (.D(\write_data_tmp_47__N_406[38] ), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[38])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i38.GSR = "ENABLED";
    LUT4 mux_841_i22_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[9]), 
         .Z(write_data_tmp_47__N_406[21])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i22_3_lut_4_lut.init = 16'h8f80;
    FD1P3AX write_data_tmp_i0_i37 (.D(\write_data_tmp_47__N_406[37] ), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[37])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i37.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i36 (.D(write_data_tmp_47__N_406[36]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[36])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i36.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i35 (.D(write_data_tmp_47__N_406[35]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[35])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i35.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i34 (.D(write_data_tmp_47__N_406[34]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[34])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i34.GSR = "ENABLED";
    LUT4 mux_841_i21_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[12]), 
         .Z(write_data_tmp_47__N_406[20])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i21_3_lut_4_lut.init = 16'h8f80;
    FD1P3AX write_data_tmp_i0_i32 (.D(\write_data_tmp_47__N_406[32] ), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[32])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i32.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i30 (.D(write_data_tmp_47__N_406[30]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(\write_data_tmp[30] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i30.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i28 (.D(write_data_tmp_47__N_406[28]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[28])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i28.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i26 (.D(write_data_tmp_47__N_406[26]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[26])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i26.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i24 (.D(write_data_tmp_47__N_406[24]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(\write_data_tmp[24] )) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i24.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i22 (.D(write_data_tmp_47__N_406[22]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[22])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i22.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i21 (.D(write_data_tmp_47__N_406[21]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[21])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i21.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i20 (.D(write_data_tmp_47__N_406[20]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[20])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i20.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i19 (.D(write_data_tmp_47__N_406[19]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[19])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i19.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i18 (.D(write_data_tmp_47__N_406[18]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[18])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i18.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i16 (.D(write_data_tmp_47__N_406[16]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[16])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i16.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i14 (.D(write_data_tmp_47__N_406[14]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[14])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i14.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i12 (.D(write_data_tmp_47__N_406[12]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[12])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i12.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i10 (.D(write_data_tmp_47__N_406[10]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[10])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i10.GSR = "ENABLED";
    LUT4 mux_841_i19_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[10]), 
         .Z(write_data_tmp_47__N_406[18])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i19_3_lut_4_lut.init = 16'h8f80;
    FD1P3AX write_data_tmp_i0_i8 (.D(write_data_tmp_47__N_406[8]), .SP(clk_c_enable_96), 
            .CK(clk_c), .Q(write_data_tmp[8])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i8.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i6 (.D(n6893), .SP(clk_c_enable_87), .CK(clk_c), 
            .Q(write_data_tmp[6])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i6.GSR = "ENABLED";
    LUT4 mux_841_i17_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[8]), 
         .Z(write_data_tmp_47__N_406[16])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i17_3_lut_4_lut.init = 16'h8f80;
    FD1P3AX write_data_tmp_i0_i2 (.D(n3299), .SP(clk_c_enable_87), .CK(clk_c), 
            .Q(write_data_tmp[2])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i2.GSR = "ENABLED";
    FD1P3AX write_data_tmp_i0_i1 (.D(n6894), .SP(clk_c_enable_87), .CK(clk_c), 
            .Q(write_data_tmp[1])) /* synthesis LSE_LINE_FILE_ID=13, LSE_LCOL=21, LSE_RCOL=6, LSE_LLINE=110, LSE_RLINE=122 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam write_data_tmp_i0_i1.GSR = "ENABLED";
    LUT4 mux_841_i9_3_lut_4_lut (.A(n6912), .B(n3646), .C(n6913), .D(write_data_tmp[1]), 
         .Z(write_data_tmp_47__N_406[8])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i9_3_lut_4_lut.init = 16'h8f80;
    FD1P3IX count_1107__i2 (.D(n21[2]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(count[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam count_1107__i2.GSR = "ENABLED";
    FD1P3IX count_1107__i3 (.D(n21[3]), .SP(clk_c_enable_96), .CD(clk_c_enable_87), 
            .CK(clk_c), .Q(count[3]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam count_1107__i3.GSR = "ENABLED";
    LUT4 mux_821_i1_4_lut (.A(write_data_tmp[40]), .B(n1897[0]), .C(n6928), 
         .D(n6947), .Z(n1856[0])) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam mux_821_i1_4_lut.init = 16'h0aca;
    LUT4 i4559_4_lut_4_lut (.A(n6946), .B(n6933), .C(n6947), .D(sck_N_335), 
         .Z(n6510)) /* synthesis lut_function=(A (C+(D))+!A (B+(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(37[15:26])
    defparam i4559_4_lut_4_lut.init = 16'hffe4;
    LUT4 i2039_1_lut (.A(write_data_tmp[46]), .Z(n3956)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam i2039_1_lut.init = 16'h5555;
    LUT4 mux_822_Mux_0_i2_3_lut (.A(x_tmp[4]), .B(x_tmp[0]), .C(cur_st[0]), 
         .Z(n2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_822_Mux_0_i2_3_lut.init = 16'hcaca;
    LUT4 i1256_1_lut (.A(cur_st[0]), .Z(nxt_st_3__N_468[0])) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(61[60:68])
    defparam i1256_1_lut.init = 16'h5555;
    CCU2D x_tmp_1106_add_4_9 (.A0(x_tmp[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5947), .S0(n37[7]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_add_4_9.INIT0 = 16'hfaaa;
    defparam x_tmp_1106_add_4_9.INIT1 = 16'h0000;
    defparam x_tmp_1106_add_4_9.INJECT1_0 = "NO";
    defparam x_tmp_1106_add_4_9.INJECT1_1 = "NO";
    FD1P3AX x_tmp_1106__i4 (.D(n47[4]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i4.GSR = "ENABLED";
    LUT4 i2_2_lut_4_lut (.A(cur_st[1]), .B(n6933), .C(cur_st[0]), .D(n6954), 
         .Z(n5988)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(82[13:14])
    defparam i2_2_lut_4_lut.init = 16'hfd00;
    FD1P3AX x_tmp_1106__i5 (.D(n47[5]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i5.GSR = "ENABLED";
    FD1P3AX x_tmp_1106__i6 (.D(n47[6]), .SP(clk_c_enable_96), .CK(clk_c), 
            .Q(x_tmp[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106__i6.GSR = "ENABLED";
    LUT4 i4511_2_lut_4_lut (.A(cur_st[1]), .B(n6933), .C(cur_st[0]), .D(\cur_st[0] ), 
         .Z(n6460)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(82[13:14])
    defparam i4511_2_lut_4_lut.init = 16'hfffd;
    LUT4 i4624_2_lut_3_lut_4_lut_4_lut (.A(n6947), .B(sck_reg_c), .C(n6904), 
         .D(n6946), .Z(clk_c_enable_7)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(80[13:14])
    defparam i4624_2_lut_3_lut_4_lut_4_lut.init = 16'h0010;
    LUT4 x_tmp_1106_mux_6_i3_4_lut (.A(n37[2]), .B(n6403), .C(n6913), 
         .D(n3646), .Z(n47[2])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i3_4_lut.init = 16'h3a0a;
    LUT4 i3_4_lut (.A(count[0]), .B(count[3]), .C(count[1]), .D(count[2]), 
         .Z(\nxt_st_3__N_472[0] )) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i3_4_lut.init = 16'hfdff;
    LUT4 i1265_3_lut (.A(cur_st[2]), .B(cur_st[1]), .C(cur_st[0]), .Z(\nxt_st_3__N_468[2] )) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(61[60:68])
    defparam i1265_3_lut.init = 16'h6a6a;
    CCU2D x_tmp_1106_add_4_7 (.A0(x_tmp[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(x_tmp[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5946), .COUT(n5947), .S0(n37[5]), .S1(n37[6]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_add_4_7.INIT0 = 16'hfaaa;
    defparam x_tmp_1106_add_4_7.INIT1 = 16'hfaaa;
    defparam x_tmp_1106_add_4_7.INJECT1_0 = "NO";
    defparam x_tmp_1106_add_4_7.INJECT1_1 = "NO";
    CCU2D x_tmp_1106_add_4_5 (.A0(x_tmp[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(x_tmp[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5945), .COUT(n5946), .S0(n37[3]), .S1(n37[4]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_add_4_5.INIT0 = 16'hfaaa;
    defparam x_tmp_1106_add_4_5.INIT1 = 16'hfaaa;
    defparam x_tmp_1106_add_4_5.INJECT1_0 = "NO";
    defparam x_tmp_1106_add_4_5.INJECT1_1 = "NO";
    LUT4 equal_198_i6_2_lut_rep_95 (.A(cur_st[2]), .B(cur_st[3]), .Z(n6933)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(38[23:34])
    defparam equal_198_i6_2_lut_rep_95.init = 16'hdddd;
    LUT4 i2_2_lut_rep_75_3_lut_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[1]), 
         .D(cur_st[0]), .Z(n6913)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(38[23:34])
    defparam i2_2_lut_rep_75_3_lut_4_lut.init = 16'hfdff;
    LUT4 i1_4_lut (.A(n3646), .B(n6932), .C(n6951), .D(\cur_st[2] ), 
         .Z(n3272[8])) /* synthesis lut_function=(A (B+(C (D)+!C !(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam i1_4_lut.init = 16'ha88a;
    LUT4 i2_3_lut_rep_91_4_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[0]), 
         .D(cur_st[1]), .Z(n6929)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(38[23:34])
    defparam i2_3_lut_rep_91_4_lut.init = 16'hfdff;
    LUT4 mux_841_i20_4_lut (.A(write_data_tmp[11]), .B(n3646), .C(n6913), 
         .D(n5266), .Z(write_data_tmp_47__N_406[19])) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(96[14] 109[16])
    defparam mux_841_i20_4_lut.init = 16'h0aca;
    LUT4 i1_2_lut_rep_82_3_lut (.A(cur_st[2]), .B(cur_st[3]), .C(cur_st[0]), 
         .Z(n6920)) /* synthesis lut_function=((B+!(C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(38[23:34])
    defparam i1_2_lut_rep_82_3_lut.init = 16'hdfdf;
    LUT4 x_tmp_1106_mux_6_i5_4_lut (.A(n37[4]), .B(n6402), .C(n6913), 
         .D(n3646), .Z(n47[4])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i5_4_lut.init = 16'h3a0a;
    LUT4 i3966_2_lut (.A(count[1]), .B(count[0]), .Z(n21[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam i3966_2_lut.init = 16'h6666;
    LUT4 mux_821_i6_4_lut_then_4_lut (.A(cur_st[0]), .B(cur_st[1]), .C(cur_st[3]), 
         .D(cur_st[2]), .Z(n6959)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B+(C+!(D))))) */ ;
    defparam mux_821_i6_4_lut_then_4_lut.init = 16'h0102;
    LUT4 i3973_2_lut_3_lut (.A(count[1]), .B(count[0]), .C(count[2]), 
         .Z(n21[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam i3973_2_lut_3_lut.init = 16'h7878;
    LUT4 mux_821_i2_4_lut (.A(write_data_tmp[41]), .B(n1897[1]), .C(n6928), 
         .D(n6947), .Z(n1856[1])) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam mux_821_i2_4_lut.init = 16'h0aca;
    LUT4 i3980_3_lut_4_lut (.A(count[1]), .B(count[0]), .C(count[2]), 
         .D(count[3]), .Z(n21[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(107[24:31])
    defparam i3980_3_lut_4_lut.init = 16'h7f80;
    LUT4 x_tmp_1106_mux_6_i6_4_lut (.A(n37[5]), .B(spi_send_N_200), .C(n6913), 
         .D(n3646), .Z(n47[5])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i6_4_lut.init = 16'hca0a;
    CCU2D x_tmp_1106_add_4_3 (.A0(x_tmp[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(x_tmp[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n5944), .COUT(n5945), .S0(n37[1]), .S1(n37[2]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_add_4_3.INIT0 = 16'hfaaa;
    defparam x_tmp_1106_add_4_3.INIT1 = 16'hfaaa;
    defparam x_tmp_1106_add_4_3.INJECT1_0 = "NO";
    defparam x_tmp_1106_add_4_3.INJECT1_1 = "NO";
    LUT4 x_tmp_1106_mux_6_i7_4_lut (.A(n37[6]), .B(spi_send_N_200), .C(n6913), 
         .D(n3646), .Z(n47[6])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i7_4_lut.init = 16'h3a0a;
    PFUMX i4760 (.BLUT(n6958), .ALUT(n6959), .C0(write_data_tmp[41]), 
          .Z(n6960));
    LUT4 i1_3_lut_4_lut_adj_46 (.A(n6901), .B(n3646), .C(n6913), .D(write_data_tmp[28]), 
         .Z(write_data_tmp_47__N_406[36])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam i1_3_lut_4_lut_adj_46.init = 16'h4f40;
    LUT4 i1_3_lut_4_lut_adj_47 (.A(n6901), .B(n3646), .C(n6913), .D(write_data_tmp[27]), 
         .Z(write_data_tmp_47__N_406[35])) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam i1_3_lut_4_lut_adj_47.init = 16'h4f40;
    LUT4 mux_822_Mux_1_i2_3_lut (.A(x_tmp[5]), .B(x_tmp[1]), .C(cur_st[0]), 
         .Z(n2_adj_602)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_822_Mux_1_i2_3_lut.init = 16'hcaca;
    LUT4 mux_821_i3_4_lut (.A(write_data_tmp[42]), .B(n2_adj_603), .C(n6928), 
         .D(n6396), .Z(n1856[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_821_i3_4_lut.init = 16'hca0a;
    CCU2D x_tmp_1106_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(x_tmp[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n5944), .S1(n37[0]));   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_add_4_1.INIT0 = 16'hF000;
    defparam x_tmp_1106_add_4_1.INIT1 = 16'h0555;
    defparam x_tmp_1106_add_4_1.INJECT1_0 = "NO";
    defparam x_tmp_1106_add_4_1.INJECT1_1 = "NO";
    LUT4 mux_822_Mux_2_i2_3_lut (.A(x_tmp[6]), .B(x_tmp[2]), .C(cur_st[0]), 
         .Z(n2_adj_603)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_822_Mux_2_i2_3_lut.init = 16'hcaca;
    LUT4 mux_821_i4_4_lut (.A(write_data_tmp[43]), .B(n2_adj_604), .C(n6928), 
         .D(n6396), .Z(n1856[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam mux_821_i4_4_lut.init = 16'hca0a;
    LUT4 mux_821_i6_4_lut_else_4_lut (.A(cur_st[0]), .B(cur_st[1]), .C(cur_st[3]), 
         .D(cur_st[2]), .Z(n6958)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam mux_821_i6_4_lut_else_4_lut.init = 16'h0002;
    LUT4 mux_822_Mux_3_i2_3_lut (.A(x_tmp[7]), .B(x_tmp[3]), .C(cur_st[0]), 
         .Z(n2_adj_604)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_822_Mux_3_i2_3_lut.init = 16'hcaca;
    LUT4 mux_821_i5_4_lut (.A(write_data_tmp[44]), .B(\nxt_st_3__N_468[1] ), 
         .C(n6928), .D(n6947), .Z(n1856[4])) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam mux_821_i5_4_lut.init = 16'h0aca;
    LUT4 i1258_2_lut (.A(cur_st[1]), .B(cur_st[0]), .Z(\nxt_st_3__N_468[1] )) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(61[60:68])
    defparam i1258_2_lut.init = 16'h6666;
    LUT4 mux_822_Mux_0_i3_3_lut_4_lut (.A(y_tmp[1]), .B(cur_st[0]), .C(cur_st[1]), 
         .D(n2), .Z(n1897[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (C (D))) */ ;
    defparam mux_822_Mux_0_i3_3_lut_4_lut.init = 16'hf808;
    LUT4 mux_822_Mux_1_i3_3_lut_4_lut (.A(y_tmp[1]), .B(cur_st[0]), .C(cur_st[1]), 
         .D(n2_adj_602), .Z(n1897[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (C (D))) */ ;
    defparam mux_822_Mux_1_i3_3_lut_4_lut.init = 16'hf808;
    LUT4 i3512_2_lut_rep_108 (.A(cur_st[1]), .B(cur_st[0]), .Z(n6946)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3512_2_lut_rep_108.init = 16'heeee;
    LUT4 equal_197_i7_2_lut_rep_90_3_lut_4_lut (.A(cur_st[1]), .B(cur_st[0]), 
         .C(cur_st[3]), .D(cur_st[2]), .Z(n6928)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam equal_197_i7_2_lut_rep_90_3_lut_4_lut.init = 16'hfeff;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cur_st[1]), .B(cur_st[0]), .C(cur_st[3]), 
         .D(cur_st[2]), .Z(spi_send_N_503)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C+(D))+!B (C+!(D))))) */ ;
    defparam i1_2_lut_3_lut_4_lut.init = 16'h010e;
    LUT4 mux_841_i11_3_lut_4_lut (.A(cur_st[1]), .B(n6920), .C(n3272[8]), 
         .D(write_data_tmp[2]), .Z(write_data_tmp_47__N_406[10])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam mux_841_i11_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_841_i15_3_lut_4_lut (.A(cur_st[1]), .B(n6920), .C(n3291), 
         .D(write_data_tmp[6]), .Z(write_data_tmp_47__N_406[14])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam mux_841_i15_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i997_2_lut_rep_70_3_lut_3_lut_4_lut (.A(cur_st[1]), .B(cur_st[0]), 
         .C(write_start), .D(n6947), .Z(n6908)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i997_2_lut_rep_70_3_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 mux_841_i23_3_lut_4_lut (.A(cur_st[1]), .B(n6920), .C(n3291), 
         .D(write_data_tmp[14]), .Z(write_data_tmp_47__N_406[22])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(85[13:14])
    defparam mux_841_i23_3_lut_4_lut.init = 16'hf1e0;
    LUT4 x_tmp_1106_mux_6_i2_4_lut (.A(n37[1]), .B(n5247), .C(n6913), 
         .D(n3646), .Z(n47[1])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/spi_oled/oled_write_data.v(105[24:31])
    defparam x_tmp_1106_mux_6_i2_4_lut.init = 16'h3a0a;
    PFUMX i4772 (.BLUT(n6976), .ALUT(spi_send_N_504), .C0(write_start), 
          .Z(n3597));
    
endmodule
